Article posted on Jun 6, 2024

Using 2D/3D Technology to Overcome Challenges of Large-Area Panel Inspection and Metrology

from Chip Scale Review

The United States is seeking to breathe new life into its domestic semiconductor packaging sector with the National Advanced Packaging Manufacturing Program (NAPMP), an initiative to “establish and accelerate domestic capacity for advanced packaging substrates and substrate materials,” according to a Commerce Department announcement from earlier this year [1]. In part, this program is the result of two very distinct trends, both of which are high-priority pursuits for governments and manufacturers. On the one hand, many nations like the U.S. are looking to shore up their semiconductor manufacturing capabilities to better protect themselves from potential geopolitical complications. Still another consideration is today’s rapidly growing demand for high-end applications like artificial intelligence (AI) and high performance computing (HPC) that are driving the need for advanced packages with 2.5 and 3D architectures. Such structures are built upon advanced integrated circuit substrates (AICS). Furthermore, the coming era of glass core substrates in advanced packaging will offer another level of challenges. The future is coming, and few want to be left behind.

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