Fan out wafer level packaging (FO-WLP) has established itself as a viable technology for high-volume manufacturing, initially, as a way to deal with shrinking die sizes, and later, in reducing package height and costs. Variations of FO-WLP, such as embedded wafer level BGA packaging (eWLB) from Infineon, integrated fanout (InFO) from TSMC and M-Series from Deca Technologies, are now commonplace among semiconductor manufactures. The same benefits that drove FO-WLP adoption, enhanced performance, and lower costs, are now driving the adoption of fan out panel level packaging, (FO-PLP). These benefits accrue from economies inherent in the use of larger rectangular panels instead of smaller round wafers. Unlike FO-WLP, which was developed on industry standard substrate sizes (the legacy of silicon wafers), FO-PLP does not have standard substrate sizes and each competing technology presents its own unique set of challenges and benefits.
This paper discusses the process challenges and solutions that were developed to address a market that could not use existing back-end of line (BEOL) technologies the way FO-WLP did. The solutions that have evolved implement a mix of ideas drawn from the printed circuit board (PCB), flat panel and FO-WLP industries. We describe an automated optical inspection techniques meant to replace laser surface analyzers (LSA) as monitoring tools, high resolution optical metrology using a novel illumination technique to control of copper redistribution layer (RDL) uniformity, and process control and feedback through defect inspection.