Apr 22 — Apr 26, 2024 Seattle, WA

Pathfinding in Optical Critical Dimension Metrology

Andy Antonelli

Andy Antonelli

Presentation at Materials Research Society (MRS) Spring Meeting & Exhibit
9:00am — 5:00pm


Semiconductor manufacturing has long relied upon optical methods for non-destructive high volume critical dimensional metrology. Optical reflectometers, ellipsometers, and interferometers from the deep ultraviolet to near infrared are essential engines of discovery. The underlying architecture and operating principles of many modern optical metrology tools are directly related to their progenitor instruments. Increased complexity and continued scaling of logic and memory devices offer new metrology challenges and force the continued evolution of these tools and the introduction of new architectures. High aspect ratio and buried structures are two general areas of concern for future devices which optical metrology must address.

High aspect ratio structures >100:1 have become an integral part of many semiconductor devices in a variety of applications. Conventional optical critical dimension metrology tools can address a subset of this need but fall short in some use cases. One potential solution lies in the extension of these techniques into the mid-infrared range.

The shift to a three-dimensional paradigm for transistor and interconnect geometries has led to an increase in the use of conformal and gap filling techniques to address reentrant features. Both random and systematic void formation are common defect modes in these processes. In some process flows, an opaque metal layer disrupts the conventional lithographic layer alignment requiring a different approach. Photoacoustic methods can be applied to address both issues. It is also possible to use photoacoustics to perform sub-optical resolution dimensional metrology of buried features.      

In this talk, we shall briefly discuss optical methods capable of addressing these challenges. The physical principles of the proposed approaches and hardware implementation will be reviewed. Several examples drawn from memory and logic process flows will be shared.