Article posted on Feb 1, 2021
In their continuing drive to pack more computing power and speed into less space, semiconductor manufacturers are using advanced packaging (AP) processes to integrate multiple die of different types within a single package and to increase input/output (I/O) connectivity for large, complex chips. The use of front-end-like processes to create ever smaller features on ever larger substrates is increasing the need for process control and inspection in AP processes. Novel materials like organic polymer dielectrics pose special challenges to conventional front-end optical technologies. Our new illumination technology, Clearfind®, specifically addresses these issues to provide high-sensitivity defect detection.
Packaging evolution
Packaging processes have evolved from relatively simple, inexpensive technologies to costly, complex processes that have adopted and adapted process technologies developed for wafer fabrication. Some of these processes are discussed in the sections below.
Wire bonding. Traditionally, packaging uses thin wires bonded between I/O pads at the edge of the chip and a wire frame that includes pins for connection to a printed circuit board. The chip and frame are encapsulated for protection from the external environment, resulting in a final package that is much larger than the chip.
Flip chip. Chip-scale processes, like flip chip, form contact pads on the top surface of the die, which, when the separated die are flipped over, mate with solder balls on a connecting package substrate. Flip-chip packages allow many more I/O connections because the entire surface of the chip, not just the edges, can be used for contacts. The resulting package is smaller than wire bonding, but usually larger than the chip.
Wafer-level processing. Wafer-level processing (WLP) uses front-end-like processes to form packaging structures on chips while they are still part of the wafer on which they are fabricated. WLP has the benefit of creating small packages – the same size as the chip – but that small size ultimately limits the space available for I/O connections.
Fan-out wafer-level processing. Fan-out wafer-level processing (FOWLP) offers increased I/O capability. Separated chips are embedded in a round substrate with space added between the chips. Overlying redistribution layers (RDL) route signals from contacts on the top surface of the chip to contacts on the top surface of the larger substrate extending beyond the area of the chip itself. The round, wafer-like form factor of the reconstituted FOWLP substrates permits the use of process equipment and handlers designed for wafer processing with minimal modification. But it also limits the size of the substrate (and therefore the number of die that it can contain), and it wastes space near the curved edges of the substrate where rectangular die/packages do not fit efficiently.
Fan-out panel-level processing. Fan-out panel-level processing (FOPLP) is similar to FOWLP except the panel substrates are not limited to wafer-like form factors. They can be rectangular, to increase spatial efficiency, and larger, to process more die per panel at lower cost per die.