Ultra High Density Interconnect Technologies and Supply Chain Readiness for AI & HPC

Heterogeneous integration and chiplets will require fine line and space interconnects, as well as low warpage materials, to achieve the required performance for various applications in the rapidly evolving landscape of Artificial Intelligence (AI) and High-Performance Computing (HPC), which have significantly increased computational and memory needs. One of the critical areas that continues to have challenges in the industry is advancing the interconnects at the organic substrate level, reason why various different approaches are being considered:

• Ultra-high density organic substrate (2.0D), bringing front-end of the line processes into the substrate/panel infrastructure to meet ultrafine Via/L/S (2/2/2 um and below).
•  Building the organic substrate at wafer level (SOW)
• Hybrid substrates:
• Bringing the well-known redistribution lines (RDLs)  to substrates using 2.xD technologies
• Bringing glass substrates to address the needs for advanced interconnects and warpage issues for large size and complex substrates.

Each of these approaches have their own limitations and challenges. This session will discuss the different alternative technologies addressing the latest developments and remaining challenges, supply chain readiness to address the next generation of interconnects.

The session will comprise of a panel of industry experts across the supply chain with global participation. Each panelist will provide a short presentation of their view on these technologies and supply chain readiness followed by a panel discussion.