Process Control Solutions for Heterogeneous Integration Through Automated Optical Inspection (AOI)

Heterogeneous Integration, using advanced packaging techniques, has rapidly gained popularity in recent years by providing an attractive alternative to monolithic ICs, where packing more transistors on a single chip is not only becoming more difficult but also more expensive. By disaggregating large die into multiple chiplets, device makers can more efficiently optimize processes to improve yield and reduce manufacturing costs. Advanced packaging has enabled the integration of these chiplets into a compact package to deliver greater functionality and higher device performance at lower cost.

Under the advanced packaging umbrella, several methodologies exist that sufficiently meet the demands of the most advanced applications. However, as the performance requirements become more stringent, there is a need to further scale down to increase interconnect density. The Critical dimensions of redistribution layers (RDLs) in Fan-Out Wafer-Level Packaging (FOWLP), Through Silicon Vias (TSV) in Silicon Interposers, Bump height/pitch in Chiplet Technology and Cu-Ox pitch in Hybrid Bonding are all being challenged to meet the requirements of the next technology node. Shrinking feature sizes are driving new requirements for higher sensitivity inspection and accurate metrology. Furthermore, with the wide array of advanced packaging technologies available today and which will be available tomorrow, the need for a flexible system that can not only perform inspection but be able to measure 2D and 3D geometries is becoming more prevalent.

In this presentation, we discuss the different technologies that can be embedded in an automated optical inspection (AOI) system to address a wide range of applications, both 2D and 3D, in the above-mentioned advanced packaging technologies.