Investigating Overlay Control Towards 2.5/3D System Integration in Back-end Lithography Processes

Since Gordon Moore’s prediction in 1965, the demands for a microchip have pushed the transistor scaling to its physical limit. Nowadays, chip manufacturers are adopting heterogeneous integration in conjunction with advanced semiconductor nodes to sustain the needs. In these efforts, various chip tilts or chiplets are integrated not only horizontally, but also vertically by stacking. In this two-point-five- and three-dimensional (2.5/3D) system integration, the technology roadmap continuously heads toward higher interconnect density, more microsystems and larger interposer size. In this work, we investigate two challenges for processing redistribution layers (RDLs) in back-end lithography. Firstly, based on the die-first approach, we simulate a unit interposer in which two chiplets are randomly placed onto it. A die-by-die alignment strategy is implemented which improves 43% in overlay (OVL) for die displacements inside the interposer. Secondly, we simulate the fabrication of large interposers in which the image layout is stitched up to 8 times (8x) of a full front-end reticle size (26x33 or 858 mm²). The stitching accuracy is managed within 560 nm in a periodic monitoring.