Chiplet Integration - Challenges and Solutions for Panel Level Packaging and Hybrid Bonding

The demand for advanced node used in high performance computing, artificial intelligence and deep learning applications, the desire to combine different device node technologies; and the need for integrated memory technologies have accelerated the trend toward heterogenous integration development and production. Panel Level Packaging (PLP) and hybrid bonding are two key technologies that can deliver these integrated packages. This presentation will provide a brief introduction to the market growth drivers and the key challenges of PLP, hybrid bonding and other wafer level packaging enablers for heterogenous integration. Solutions to help monitor the manufacturing process and address the specific key challenges will be discussed. The presentation will conclude with a use case demonstrating the power of connected thinking - how process control analytics can provide feedforward adjustment to subsequent manufacturing steps and explore the importance of chiplet genealogy information.