Abstract
Heterogeneous integration combines multiple chips with different functionalities and from different silicon nodes inside one package, ranging in size from 75mm x 75mm to 175mm x 175mm. But as with any new technology, heterogeneous integration comes with its own set of unique challenges. For starters, package sizes are expected to grow significantly due to the number of components in each integrated package. The problem: these significantly larger packages would typically require multiple exposure shots to complete the lithography steps for the package. Furthermore, the process of adding multiple redistribution layers (RDL) may cause stress to both the surface and inside of the substrate. Formation changes experienced by the panel, as a result of thermal, high-stress and other fan-out processes, shift the design location from its nominal coordinates; this causes inaccurate overlay and low-overlay yield in the lithography process. And then there is the matter of tightening resolution requirements. RDL layers in AICS will require a resolution of 3µm and will eventually move toward a resolution of 1µm. To address these challenges, and better serve the heterogeneous integration process, an extremely large exposure field, fine-resolution lithography solution was proposed to enable packages up to 250mm x 250mm without the need for image stitching, while meeting the overlay and critical dimension uniformity requirements for these packages.
