The road to the future is not always a smooth, trouble-free drive. Along the way, there may be unforeseen detours, potholes and accidents, each one capable of setting progress back. But for those behind the wheel, those obstacles are just a part of the journey.

Such is the case for the automotive industry as it continues to steer away from gas-powered vehicles and turn toward hybrid and electric vehicles. To accomplish this, manufacturers of power devices are opting to use wide-bandwidth compound semiconductors like SiC and GaN. The reason: compound semiconductors accommodate higher voltages, faster switching speeds and lower losses than traditional silicon-based power devices.

For the purpose of our three-part series, we have been focusing on SiC power devices, the challenges presented by trench-based architectures that reduce on-resistance and increase carrier mobility, and the need to accurately measure epi layer growth and the depth of implant layers. Before we move onto the details of this blog, let’s take a quick look back at the previous two blogs.

You don’t have to be a dedicated follower of the transportation industry to know it is in the early stages of a significant transition, away from the rumbling internal combustion engine to the quiet days of electric vehicles. The signs of this transition are right there on the streets in the form of electric-powered buses, bikes and cars. The road to our electric future is before us, but we won’t be getting there without compound semiconductors like SiC.

Manufacturers in the automobile and clean energy sectors want more efficient power devices that can accommodate higher voltages, possess faster switching speeds and offer lower losses than traditional silicon-based power devices, something SiC power devices with trench structures can deliver.

But while trench-based architectures offer reduced on-resistance and increase carrier mobility, they bring along increased complexity. For manufacturers of SiC power devices, the ability to accurately measure epi layer growth and the depth of implant layers in these trenches is of considerable concern, especially when faced with ever-increasing fabrication complexity.

In the previous blog in this series, we explored how using an FTIR-based system allows for the direct modeling of carrier concentrations and film thickness, thus enabling SiC power device makers to better measure epi layer growth, implant layers and composition. In this installment, we explore how manufacturers of SiC power devices with trench-based structures measure trench depth and bottom and top critical dimension (CD) by using an optical critical dimension (OCD) metrology system designed for specialty devices.

The figures alone are impressive: SiC power devices are experiencing an annual average growth rate approaching 34% through 2027, according to the Yole Group. However, the potential for this amongst other compound semiconductor-based power devices such as gallium nitride (GaN) to change the world around us is even more impressive.

Thanks to the role that SiC-based devices play in the increased electrification of automobiles and the sustainable energy movement, the effort to make this world a cleaner, greener place is no longer a wished-for science fiction fantasy. It may one day be our reality. Perhaps even soon.

Manufacturers in the automobile and clean energy sectors want power devices that are more efficient and can accommodate higher voltages, faster switching speeds and lower losses than traditional silicon-based power devices. To accomplish this, they are turning to higher efficiency silicon carbide (SiC)-based devices.

When it comes to SiC power devices, most manufacturers have adopted a trench-based architecture. This reduces on-resistance and increases carrier mobility. However, these improvements come at the expense of rising fabrication complexity.

To address this issue, high-volume manufacturers of SiC power devices are, at several key steps, adopting inline process control methods, including optical metrology techniques like Fourier transform infrared (FTIR). With a system supporting FTIR optical metrology at their disposal, manufacturers can more accurately measure epi layer growth and the depth and accuracy of implanted dopants across the wafer, key challenges posed by the increased fabrication complexity of SiC power devices. In this blog, we’ll discuss how FTIR technology can help manufacturers successfully address these challenges.

It is no mystery that the semiconductor industry is always advancing, with specifications becoming increasingly stringent as defects become increasingly more difficult to discover. This is especially true in the case of the most advanced nodes, where ever-smaller flaws and deformities can result in a killer defect.

To solve this More than Moore mystery, you do not need to employ the detective skills of Sherlock Holmes. You need the metaphorical equivalent of the pipe-smoking hero’s magnifying glass to find the particles, scratches, pits and air pockets hiding in the shadows.

Take the critical dimensions of trenches and vias, for example. As they shrink, the size of a particle or scratch that can potentially result in a killer defect decreases in size as well, making sensitivity an increased priority for bare wafer inspection — on the frontside and backside, at the edge and in the notch.

With an eye on evolving requirements for advanced node bare wafers, manufacturers are seeking inspection solutions with automatic defect classification (ADC) capabilities to perform outgoing quality assurance for wafers, including polished wafers and those with silicon epitaxial layers. Armed with these ADC capabilities, customers can significantly reduce the need for time-consuming and costly manual review.

The frontside, bulk, backside, edge and notch — each of these areas needs to be inspected to ensure the quality of the silicon wafer and the successful fabrication of advanced devices on the wafer. We’ll start with frontside and bulk before moving onto backside, edge and notch inspection, the main focus of this blog.

Wind power. Rail. Solar energy. And, perhaps most significantly, electric and hybrid vehicles. Together, these four forces are among the major demand drivers for power devices.

While silicon (Si) still plays a role in power devices, wide-bandgap compound semiconductors like silicon carbide (SiC) and gallium nitride (GaN) are particularly well-suited for power devices thanks to their higher electron mobility, higher critical electric field and higher thermal conductivity. However, as new structures and larger wafer sizes become the norm for power devices, they bring with them distinct manufacturing challenges.

Today, the industry is transitioning from 150mm to 200mm wafers for SiC- and GaN-based devices and 200mm to 300mm wafers for Si-based devices. The reason: larger wafer sizes may help reduce the cost of fabrication. As the wafer size transition occurs, it is important to have a metrology tool that can measure a larger number of data points across the wafer without impacting the overall fab throughput. A loss of throughput adds to cost-of-ownership and may erase savings earned from transitioning to larger wafers.

In recent years, power semiconductor applications have expanded from industrial and consumer electronics to renewable energy and electric vehicles. Looking to the future, the most promising power semiconductor devices will be insulated gate bipolar transistor (IGBT) and power metal oxide semiconductor field effect transistor (power MOSFET) modules.

During the manufacturing of these devices, metal films are deposited on the die of MOSFET and IGBT power devices. These layers of film have two main functions: they connect the elementary cells constituting the power dies to the source (power MOSFET) or emitter (IGBT) and allow for the welding of bond wires on the chip or for the solder bonding, facilitating thermal conduction. Because power devices run high currents at high-operating temperatures, the metal layers need to be properly controlled for electrical properties and thickness to enhance thermal conductivity.

Furthermore, power devices are transitioning from 6-inch to 8-inch wafers; this is happening at the same time as process windows are shrinking. As a result, measuring multi-layer metal thickness accurately and characterizing the uniformity of metal film deposition at the wafer edge has become increasingly important. For example, the front side of wafers requires deposition of a thick metal layer, typically 5µm or more of aluminum alloy. The uniform coverage of aluminum to conduct high currents across the entire wafer is key to device yield and reliability.