Semiconductor manufacturing creates a wealth of data – from materials, products, factory subsystems and equipment. But how do we best utilize that information to optimize processes and reach the goal of zero defect manufacturing?

This is a topic we first explored in our previous blog, “Achieving Zero Defect Manufacturing Part 1: Detect & Classify.” In it, we examined real-time defect classification at the defect, die and wafer level. In this blog, the second in our three-part series, we will discuss how to use root cause analysis to determine the source of defects. For starters, we will address the software tools needed to properly conduct root cause analysis for a faster understanding of visual, non-visual and latent defect sources.

Whether the discussion is about smart manufacturing or digital transformation, one of the biggest conversations in the semiconductor industry today centers on the tremendous amount of data fabs collect and how they utilize that data.

While chip makers are accumulating petabytes of data across the entire semiconductor process, a question arises: how much of that information is being fully utilized? The answer may be around 20%, according to the Semiconductor Engineering article “Too Much Fab and Test Data, Low Utilization.” Unfortunately, this poses a challenge because fab end customers are demanding highly reliable chips, in other words, chips with zero escaping defects and which offer manufacturers clear genealogy and traceability.

Many of you reading this work for companies that have started or are planning digital transformations. To do this, these companies will need to better integrate the data they collect — and that includes data from materials, products, processes, factory subsystems and equipment.

For smart manufacturing to truly live up to its potential, manufacturers will need inline automation that takes complete advantage of the analytics their monitoring systems generate, analytics which can be fed back to the process tools, manufacturing execution systems and other factory systems in real time. Working in concert, these integrated systems are essential to creating a zero defect manufacturing environment.

In the world of smart manufacturing, manufacturers will be tasked with providing timely total solutions to detect and classify defects using inspection and metrology tools, conduct root cause analysis to determine the source of said defects and, finally, employ process control and equipment monitoring using run-to-run and fault detection and classification software solutions to prevent defects from reoccurring.

In this blog, the first in our three-part series “Achieving Zero Defect Manufacturing,” we will focus on detecting and classifying defects. We will start by looking at solutions at the defect level before moving on to the die level and the wafer level.

The road to the future is not always a smooth, trouble-free drive. Along the way, there may be unforeseen detours, potholes and accidents, each one capable of setting progress back. But for those behind the wheel, those obstacles are just a part of the journey.

Such is the case for the automotive industry as it continues to steer away from gas-powered vehicles and turn toward hybrid and electric vehicles. To accomplish this, manufacturers of power devices are opting to use wide-bandwidth compound semiconductors like SiC and GaN. The reason: compound semiconductors accommodate higher voltages, faster switching speeds and lower losses than traditional silicon-based power devices.

For the purpose of our three-part series, we have been focusing on SiC power devices, the challenges presented by trench-based architectures that reduce on-resistance and increase carrier mobility, and the need to accurately measure epi layer growth and the depth of implant layers. Before we move onto the details of this blog, let’s take a quick look back at the previous two blogs.

You don’t have to be a dedicated follower of the transportation industry to know it is in the early stages of a significant transition, away from the rumbling internal combustion engine to the quiet days of electric vehicles. The signs of this transition are right there on the streets in the form of electric-powered buses, bikes and cars. The road to our electric future is before us, but we won’t be getting there without compound semiconductors like SiC.

Manufacturers in the automobile and clean energy sectors want more efficient power devices that can accommodate higher voltages, possess faster switching speeds and offer lower losses than traditional silicon-based power devices, something SiC power devices with trench structures can deliver.

But while trench-based architectures offer reduced on-resistance and increase carrier mobility, they bring along increased complexity. For manufacturers of SiC power devices, the ability to accurately measure epi layer growth and the depth of implant layers in these trenches is of considerable concern, especially when faced with ever-increasing fabrication complexity.

In the previous blog in this series, we explored how using an FTIR-based system allows for the direct modeling of carrier concentrations and film thickness, thus enabling SiC power device makers to better measure epi layer growth, implant layers and composition. In this installment, we explore how manufacturers of SiC power devices with trench-based structures measure trench depth and bottom and top critical dimension (CD) by using an optical critical dimension (OCD) metrology system designed for specialty devices.

The figures alone are impressive: SiC power devices are experiencing an annual average growth rate approaching 34% through 2027, according to the Yole Group. However, the potential for this amongst other compound semiconductor-based power devices such as gallium nitride (GaN) to change the world around us is even more impressive.

Thanks to the role that SiC-based devices play in the increased electrification of automobiles and the sustainable energy movement, the effort to make this world a cleaner, greener place is no longer a wished-for science fiction fantasy. It may one day be our reality. Perhaps even soon.

Manufacturers in the automobile and clean energy sectors want power devices that are more efficient and can accommodate higher voltages, faster switching speeds and lower losses than traditional silicon-based power devices. To accomplish this, they are turning to higher efficiency silicon carbide (SiC)-based devices.

When it comes to SiC power devices, most manufacturers have adopted a trench-based architecture. This reduces on-resistance and increases carrier mobility. However, these improvements come at the expense of rising fabrication complexity.

To address this issue, high-volume manufacturers of SiC power devices are, at several key steps, adopting inline process control methods, including optical metrology techniques like Fourier transform infrared (FTIR). With a system supporting FTIR optical metrology at their disposal, manufacturers can more accurately measure epi layer growth and the depth and accuracy of implanted dopants across the wafer, key challenges posed by the increased fabrication complexity of SiC power devices. In this blog, we’ll discuss how FTIR technology can help manufacturers successfully address these challenges.