I find myself educating colleagues and customers alike about misconceptions surrounding the general field of ADC. Here are some classics:
- Automatic v. Automated Defect Classification: People frequently believe the “A” in ADC is for “automatic” and have a perception that an ADC system requires no human interaction whatsoever. The truth is that an ADC solution is no different from any other tool on the manufacturing floor. Just like an etcher or CMP system, ADC executes a recipe and produces a result. Also, like other tools, that recipe needs to be created by a tool owner and from time to time needs to be adjusted as processing changes are implemented.
- ADC is hard to configure: Setting up ADC classifier is like training your operator. Just as you would subject the human trainee to multiple examples of defects, ADC systems need a similar learning session. Again, like a human trainee you’d want to test their ability to learn and based on this test make minor adjustments if needed. Modern ADC solutions are built with an intuitive UI designed to guide you through the natural steps of collecting/managing samples, configuring image detection, setting up classifiers, and verifying the results. The biggest difference verses training a human is that you only need to train a single ADC system, not a small army of human reviewers.
- ADC classifier performance is unpredictable: A well represented set of samples, and clearly defined and visually different classes, is key to both ADC and operator. An ADC classifier is very predictable when that’s the case.
- ADC is perfect: Like a human operator, ADC is not perfect. If an operator is confused on certain samples, then ADC will most likely be, too.
Analysts are projecting strong growth in advanced packaging, with CAGR through 2026 approaching 7% across the segment; much higher for certain high-end technologies, including 3D stacking, embedded die, and fan-out. Outsourced assembly and test (OSAT) firms, which package finished die manufactured by independent device manufacturers (IDM) and foundries, will be challenged by the complexity of the advanced packaging processes and will face stiff competition, in many cases from their own customers. If they are to thrive, or perhaps just survive, they will need to embrace smarter manufacturing approaches.
The historical division between front-end device manufacturing and back-end packaging/testing is the result of their vastly different cost structures and process complexity. The relative simplicity of the back-end process led OSATs to compete primarily on price, seeking always to minimize costs and maximize volume. Simple processes were simple to control. The acquisition, storage, and analysis of process data were costs to be avoided wherever possible. Advanced packaging processes have introduced a host of new variables that must be controlled to ensure process yield and product reliability. Process data is no longer a cost to be avoided, but should be considered an essential asset to be leveraged to maximize profitability.
Meanwhile, as they accommodate increasingly complex processes, OSATs confront encroachment in their markets by sophisticated competitors who may also be their customers – IDMs and foundries who have outsourced a significant portion of their production to OSATs but have also maintained their own internal back-end capabilities. Advanced packaging processes have been described as the migration of front-end like processes to traditionally back-end applications. With this evolution, the advantage device manufacturers once had, by outsourcing assembly and test to avoid diluting their expertise with low-value processes, has greatly diminished. More importantly, these customers-turned-competitors are already comfortable with managing complex processes – they wrote the book. In addition to IDMs and foundries, substrate and printed circuit board (PCB) suppliers, electronic manufacturing services (EMS), original design manufacturers (ODM), and others see the opportunity presented by the significant growth forecasted for advanced packaging.
Data is the life blood of smarter manufacturing – acquiring it, storing it, organizing it, analyzing it, sharing it. Without leveraging it you are not just blind; in the competitive environment of semiconductor manufacturing, you will probably not survive. OSATs are not new to data collection and management. After all, testing is part of their name. But test data is product/function focused. In its simplest form it is go/no go. Functional testing may go beyond that, to measure how well it works, if for no other reason than to identify the best devices and sell them for premium prices. Smarter manufacturing requires data on a whole new scale – data that is both deep and broad.
In their continuing drive to pack more computing power and speed into less space, semiconductor manufacturers are using advanced packaging (AP) processes to integrate multiple die of different types within a single package and to increase input/output (I/O) connectivity for large, complex chips. The use of front-end-like processes to create ever smaller features on ever larger substrates is increasing the need for process control and inspection in AP processes. Novel materials like organic polymer dielectrics pose special challenges to conventional front-end optical technologies. Our new illumination technology, Clearfind®, specifically addresses these issues to provide high-sensitivity defect detection.
Packaging evolution
Packaging processes have evolved from relatively simple, inexpensive technologies to costly, complex processes that have adopted and adapted process technologies developed for wafer fabrication. Some of these processes are discussed in the sections below.
Wire bonding. Traditionally, packaging uses thin wires bonded between I/O pads at the edge of the chip and a wire frame that includes pins for connection to a printed circuit board. The chip and frame are encapsulated for protection from the external environment, resulting in a final package that is much larger than the chip.
Flip chip. Chip-scale processes, like flip chip, form contact pads on the top surface of the die, which, when the separated die are flipped over, mate with solder balls on a connecting package substrate. Flip-chip packages allow many more I/O connections because the entire surface of the chip, not just the edges, can be used for contacts. The resulting package is smaller than wire bonding, but usually larger than the chip.
Wafer-level processing. Wafer-level processing (WLP) uses front-end-like processes to form packaging structures on chips while they are still part of the wafer on which they are fabricated. WLP has the benefit of creating small packages – the same size as the chip – but that small size ultimately limits the space available for I/O connections.
Fan-out wafer-level processing. Fan-out wafer-level processing (FOWLP) offers increased I/O capability. Separated chips are embedded in a round substrate with space added between the chips. Overlying redistribution layers (RDL) route signals from contacts on the top surface of the chip to contacts on the top surface of the larger substrate extending beyond the area of the chip itself. The round, wafer-like form factor of the reconstituted FOWLP substrates permits the use of process equipment and handlers designed for wafer processing with minimal modification. But it also limits the size of the substrate (and therefore the number of die that it can contain), and it wastes space near the curved edges of the substrate where rectangular die/packages do not fit efficiently.
Fan-out panel-level processing. Fan-out panel-level processing (FOPLP) is similar to FOWLP except the panel substrates are not limited to wafer-like form factors. They can be rectangular, to increase spatial efficiency, and larger, to process more die per panel at lower cost per die.
Fan-out wafer level packaging (FOWLP) is a popular new packaging technology that allows the user to increase I/O in a smaller IC size than fan-in wafer level packaging. Market drivers such as 5G, IoT, mobile and AI will all use this technology. According to Yole Développement’s analysis, the fan-out packaging market size will increase to $3 billion in 2022 from $2.44 hundred million in 2014, validating the market requirement for fan out packaging. While FOWLP has been used for many years, there is still a relentless drive to reduce the cost, and fan-out panel level packaging (FOPLP) has been proposed as one possible solution. FOPLP allows users to put more chips on a substrate, meaning more product output and a higher substrate utilization percentage. According to Yole’s analysis, the FOPLP market size will increase to $2.79 hundred million with 79% CAGR, showing that more people are adopting FOPLP.
FOPLP has many advantages and low cost potential, but it faces significant process challenges, such as die placement error and substrate warpage control. One of the key challenges is the trade-off between overlay, yield, and throughput during the lithography processing steps. A user exposes multiple dies per exposure shot to increase throughput, but this can result in lower overlay yield because of “pick and place” die placement error. To overcome the low yield issue, each die needs to be aligned, but this impacts throughput, so a compromise is required. To find the balance point between throughput and overlay is one of the biggest challenges for FOPLP.
In this paper we address the tradeoff between throughputs and overlay yield, we demonstrate an integrated feedforward adaptive shot solution. This feedforward approach uses a third party metrology system to measure reconstituted panel die location data and sends the data to the stepper via a network. With feedforward algorithm technology, the stepper uses smart adaptive shot technology to generate an optimized variable shot size layout. This layout ensures the overlay yield is within specification with the minimum number of exposure steps. With feedforward adaptive shot technology, the user can maximize the throughput of the stepper and ensure the overlay yield at the same time.
Key words: advanced packaging, die placement error, FOWLP, FOPLP, overlay, yield, feedforward.
AI and ML have great potential in many areas of the semiconductor manufacturing process, ranging in scale from improving the performance of individual tools to managing an entire fab and optimizing the global supply chain
Semiconductor manufacturers are increasingly challenged to measure and inspect new, smaller, and more complex 3D structures. Optical critical dimension (OCD) metrology has the fundamental capability needed for the measurements, but obtaining accurate results depends on deterministic physical modeling procedures that can be time-consuming and expensive. Artificial intelligence (AI) and machine learning (ML) techniques offer much faster solutions in many applications. Though AI and ML are unlikely to replace model-based measurements, they offer complementary strengths, suggesting that the best solutions will involve some combination of the two techniques.
It is well understood that advanced packaging applications require high performance, low cost, increased functionality and improved reliability that 2.5D and 3D packaging solutions provide. Fan-out panel-level packaging (FOPLP) is one of the technologies that has the potential to meet these packaging requirements. Similar to fan-out wafer-level packaging (FOWLP), FOPLP processes reconstitute die on a substrate, in this case a rectangular platform that can be significantly larger than the standard 300mm diameter wafer form. In the reconstitution process, die are displaced from their nominal grid locations during the epoxy molding compound process and sometimes during subsequent processing steps. This fan-out technology delivers more space for redistributed I/O connections, providing increased flexibility for homogeneous and heterogeneous integration. Importantly, the larger panel format can support more packages per substrate than the 300mm wafer form, and the final package size can be increased by adding space between the die.
Although FOPLP processing has many advantages, it also faces significant challenges. One critical challenge is die placement error, which occurs when die are positioned during the reconstitution and molding process. These placement errors are amplified with the larger panel format when compared to reconstituted wafers, and errors of 50μm or more are not unusual. In order to guarantee acceptable yield, these errors must be corrected during the lithography process using site-by-site corrections. Conducting metrology and site-by-site exposures on the lithography system is very time consuming. Substrate alignment and error correction may be calculated using global alignment, but this correction does not accommodate nonlinear die placement errors. It has become clear that only site-by-site corrections can deliver the overlay required to maintain good yield. Executing site-by-site alignments in the stepper reduces throughput and increases cost enough to make that approach to FOPLP processes impractical. A new approach uses an external metrology tool to capture die placement error data from a panel and feeds that information forward. The “feed-forward” solution optimizes the stepper, site-by-site, for X, Y and rotation offsets, during exposure. Visualization of the metrology data allows the user to characterize upstream and downstream processes. Moreover, analytical capabilities predict yield as a function of exposure field size, thereby allowing the user to balance throughput against yield in real time. This solution can significantly increase stepper throughput, reduce cost and increase productivity while ensuring high yield.
Die placement challenges
Generating reconstituted panel substrates creates translational and rotational die placement errors. The “pick and place” process itself introduces initial errors that are exacerbated during the mold process, and by instability of the mold compound throughout repeated processing cycles. With redistribution layer (RDL) features currently achieving dimensions as small as 2μm, die placement measurements and pattern overlay registration requirements are continuing to tighten. As a result, the position of the die must be measured before each exposure in the lithography system to ensure accurate registration with the underlying layer. Displacement errors can be measured in the lithography tool, but these measurements are slow, typically taking as much time as the exposure itself. Transferring the measurement operation to a parallel, independent metrology system and feeding corrections to the stepper, however, can double throughput. Figure 1 illustrates the use of this exposure/measurement loop to increase productivity. The die placement measurements and analysis can be repeated, if required, after each layer is exposed, to correct for any errors introduced in that step. In addition to feed-forward corrections, the software algorithm analyzes the displacement errors to predict yield (based on a user designated limit for acceptable registration error) for exposure fields of varying sizes. The method requires tight integration of the stepper and measurement system with the controlling software algorithm.
Coordinate systems; measurement accuracy
A previous study [1] looked at wafer substrates and focused on proving that automated optical inspection (AOI) feed-forward data could correct for the predefined die placement offsets. It established the AOI feed-forward accuracy to be within +/-2μm. The work described below uses a 510mm x 515mm x 1.1mm rectangular glass panel as the test vehicle to match the stepper and AOI panel stage grids and measure the AOI accuracy. The test panel was patterned using the same method as the wafer study. The test reticle used a single die “Pad” image, which was patterned across the entire panel. The pad test pattern (Figure 2), with no offsets, was then measured using the stepper and AOI system at two points per die (top and bottom).
Figure 1: The optimized stepping process loop includes: 1) measurement of die displacement errors outside the stepper; 2) Site correction calculations/yield modeling; and 3) exposure.
Figure 2: Pad test pattern showing two die.
The lithography system (JetStep System, Onto Innovation) supports panel sizes up to 720mm x 600mm. It uses pattern recognition alignment, allowing the user to train the system to recognize and align on any unique pattern within the field of view. The alignment system can measure the X, Y position of die patterns across the panel, a process often referred to as “mapping.” The AOI system (Firefly System, Onto Innovation) uses a similar pattern recognition alignment method to assess die placement error. Using the stepper and AOI alignment site measurements from the test vehicle panel, a mathematical algorithm was applied to align the stepper and AOI coordinate systems. Once a common grid coordinate system was established, the stepper stage was considered as the reference and the AOI system was compared to this reference using simple scatter plots (Figure 3). The measurements were repeated three times to confirm repeatability. In all three cases, accuracy of the AOI system was within +/-2.3μm of the stepper reference. Figure 4 shows histograms of the dX and dY distributions for R1. Table 1 summarizes the statistical data for each run.
Figure 3: Scatter plots stepper vs. AOI, for three runs: a) R1, b) R2, c) R3.
Figure 4: Test vehicle AOI error distributions R1 for a) dX, and b) dY.
Die placement error measurement
With the accuracy of the measurements and the correspondence between the exposure and measurement coordinate systems established, it is possible to evaluate the placement errors of die on FOPLP panels. Dummy die embedded in molding compound to form a FOPLP substrate were supplied courtesy of ESWIN. Measurements of two points for every die, top and bottom, allowed the system to calculate translation (X,Y) and rotation (ϴ) offsets for each. The software algorithm generates “heat maps” that visualize the dummy measurements before corrections are applied (Figure 5). Histograms of the X and Y placement errors and rotational errors (Figure 6) show the distributions of these measurements. The multimodal distributions of the dX and dY histograms reflect the nonlinear die placement errors observed in the heat maps. This nonlinear error can be attributed to the epoxy molding compound (EMC) curing process, which is typical for most FOPLP reconstituted panel processing. The disruptive EMC curing effect renders the typical global alignment solution used by lithography tools useless, as it assumes linear corrections for scaling, rotation, or orthogonality. Only site-by-site corrections can accommodate these types of errors. To apply site-by-site corrections, each exposure needs to be matched to the local errors to provide good overlay.
Table 1: Summary of dX, dY error statistics for R1,
R2, R3.
Figure 5: Die placement error (mm) a) dX, and b) dY heat maps.
Data analysis, yield prediction and throughput
The process specifies overlay errors less than +/-15μm. As long as the measured errors are within the correction capability of the stepper, it is possible to yield 100% by correcting each die, so-called “die-by-die” exposure individually, but this imposes an unacceptable penalty on stepper throughput. Increasing the size of the exposure to cover multiple die will Increase throughput, but reduces the ability to correct for individual die placement errors. By evaluating virtual exposures for different field sizes – and with each exposure corrected to optimize yield within the exposed field – it is possible to maximize process yield (defined as the percentage of die that will meet the overlay specification) and quantitatively evaluate trade-offs between yield and throughput for different field sizes. Only by having real-time data analysis can the user identify the correct settings and react to out-of-control situations without impacting yield.
For the panels evaluated, the software algorithm predicted 100% yield with a field size of 3×3 (Figure 7). The dX data was worse than the dY data, but all die placements were within the +/-15μm via to pad overlay specification. As the stepper field size was increased to 6×6 die, the yield drops to 99.42% as some of the die dX overlay errors exceeded the +/-15μm specification (Figure 8).
The software algorithm’s yield prediction has been compared to actual customer product overlay measurements, confirming the accuracy of the prediction is within 0.2% of final overlay results. This result provided the user with confidence that AOI pre-measurement of panels with product die can be used to determine the optimum field size, throughput and yield prior to coating the panel with polyimide or photoresist. This has significant advantages in both cost and process development. For example, polyimide processing is normally a non-reworkable process step and overlay errors at this stage result in scrapped die. Typically, if there is a die placement error that exceeds the specification of the multi-die exposure field it will only be observed after fully processing the polyimide lithography and measuring overlay. By this time, it would be too late to recover, requiring the die to be scrapped. With the ability to pre-measure and predict the yield with the AOI system and software algorithm, low yield could be avoided by reducing the field size. Moreover, the heat map and histogram data could be sent “upstream” to the EMC process engineer to address the root cause of molding process die placement error excursion.
Figure 6: a) dX (mm), b) dY (mm), and c) rotation (rad) data histograms.
Figure 7: Predicted a) dX and b) dY overlay data histogram (mm) for 3 X 3 field, 100% yield.
Figure 8: Predicted a) dX and b) dY overlay data histogram (mm) for 6×6 field size, where some die are out of
specification, thereby reducing yield.
Summary
It is clear from the experimental data that the calculated feed-forward site corrections provided the stepper with the ability to automatically compensate for die placement error. This is a significant improvement over the industry standard, where steppers use a simple linear model approach. Application of the site corrections, with larger field sizes during stepping, increased the lithography throughput significantly from 3 x 3 to 6 x 6 with low impact on yield, 100% to 99.42% respectively. This will naturally deliver commensurate reductions in cost of ownership. The visualization of the die placement data using heat maps, histograms, vector plots, etc., provides the process engineer with the ability to optimize and predict the impact of stepper field size on production yield and throughput. Moreover, this revolutionary capability provides foresight, enabling the user to quickly feed data to upstream and downstream processes to prevent costly rework and scrapped product. Future software developments will provide a method to dynamically balance throughput with yield.
Acknowledgements
This article is based on a paper presented at the International Wafer Level Packaging Conference (IWLPC) 2019. The authors wish to thank Amr Hafez, Phil Convey and Karie Li for their work on the software algorithm, which was key to delivering the die placement error solution, Burhan Ali for his support of the AOI system, and Corey Shay for his stepper support. Finally, we thank ESWIN, which provided the dummy die panels necessary for the yield prediction tests.
References
1. K. Best, M. Marshall, “Advanced packaging metrology and lithography that overcomes FOWLP/FOPLP die placement error,” IWLPC 2018.
2. K. Ruhmer, “Lithography challenges for 2.5D interposer manufacturing,” ECTC 2014, Orlando, FL, USA.
3. R. McCleary, “Panel-level advanced packaging,” ECTC 2015, Las Vegas, NV.
4. K. Ruhmer, P. Cochet, R. McCleary, “Panel-based fan-out packaging to reduce Costs,” SMTA/Chip Scale Review, IWLPC, San Jose, CA, Nov. 11-13, 2014.
5. K. Ruhmer, P. Cochet, R. McCleary, N. Chen, “High-resolution patterning technology to enable panel-based advanced packaging,” IMAPS 2014, San Diego, CA, Oct. 13-16, 2014.
Biography
Keith Best is Director of Applications Engineering for the lithography business unit at Onto Innovation, Wilmington, MA. He has over 30 years of semiconductor processing experience and has held a variety of Applications positions for both device manufacturing and capital equipment companies. Keith received his BSc Honors degree in Materials Science from the U. of Greenwich, UK. He holds 16 US patents in the areas of photolithography and process integration. Email [email protected]