The semiconductor industry is constantly marching toward thinner films and complex geometries with smaller dimensions, as well as newer materials. The number of chemical mechanical planarization (CMP) steps has increased and, with it, a greater need for within-wafer uniformity and wafer-to-wafer control of the thin film layers.

Process engineers have typically adopted over-polishing and re-working as part of the standard operating procedure to reach the desired end point and required film uniformity on the wafers. This is because the current generation of integrated metrology toolsets are based on relatively simple optical techniques, such as reflectometry, and do not have the inherent high resolution offered by off-line techniques, such as ellipsometry, which are technically complicated and cost prohibitive to implement as integrated solutions on process tools.

When it comes to thin film residuals, the current steps in the CMP process — with both over-polish and rework steps playing prominent roles — are inefficient and result in lower yields.

The next generation of CMP tools from leading suppliers are targeting a 100% increase over current throughput, going from 80 to 100 wafers per hour to more than 200 wafers per hour. In order to achieve the expected increase in throughput, the time currently being spent on offline feedback and rework is simply not feasible as a part of a process control strategy.

If the true potential of these next-gen CMP tools is to be reached, these CMP tools must be installed with integrated metrology capable of measuring extremely thin films and accurately reporting the end point, thereby eliminating the need for offline metrology. With this requirement, integrated metrology modules will need additional input and data processing capability to measure sub-50Å residual films in a CMP environment.

A recent internal study between Onto Innovation and Micron indicates that a hybrid metrology approach can be effective in improving the measurement accuracy of thinner films. This approach combines measurements from different steps in the process and then uses that information to enhance the data analysis of the integrated metrology tool via machine learning. Such an approach provides accurate film thickness discrimination and enables the proper end point in CMP. This reduces the need for over-polishing and significantly reduces the rework rate.

Trends in advanced device fabrication require combined lithography-etching multi-patterning sequences and self-aligned multi-patterning to form devices’ finest features at subwavelength dimensions.

As EUV lithography (13.5 nm) progresses to larger numerical apertures and new thin resists, new multipatterning sequences must be developed with mutually compatible resists and proximal layers to avoid resist poisoning, encourage adhesion, and enable expended materials to be easily removed without harming similar materials. Subsequent pattern transfers to form device structures by etching require mutually etch-exclusive resists, masking, and spacer materials, where each can be selectively removed by an etch process that leaves the other materials unaffected.

Materials’ resistances or susceptibilities to different etch chemistries are ultimately determined by their etching performances. Material etching rates are defined by the differences in thickness measurements made prior to and after exposure to specific wet or dry etchants for specific time intervals. Selectivity is a relative comparison of the ratio of different materials’ etching rates in an etchant where, for example, a patterning hardmask must have low selectivity compared to the underlying material that it protects.

The demand for smartphone cameras, video conferencing, surveillance and autonomous driving has fueled explosive growth of CMOS image sensor (CIS) manufacturing in the last decade. While CIS becomes an increasingly important element in the production of today’s consumer electronics, there are unique challenges in production that must be addressed. As pixel sizes shrink, we see an inverse relationship with the number of pixels in the array increasing, which presents challenges for process control of the sensor, especially as it relates to the color filter array (CFA) and on-chip lens (OCL). With the push to 1µm and below pixel sizes, the ability to find sub-micron defects and macro-level variations within the pixel array is even more important to ensure uniform and unobstructed responses throughout the active pixel sensor array (APS).

CIS is unique from other semiconductor devices because it converts light energy into electrical signals. It is manufactured on silicon wafers similar to semiconductors and follows typical back-end packaging processes such as grinding, sawing, and electrical testing. A typical CIS device has an ASP region in the center of the die with electrical I/Os (bondpads) on the periphery. Deionized water is often used to clean up mobile contamination left behind during the wafer thinning or die singulation process which has an inherent risk of staining or leaving a residue on the APS that affects the quantization of light and is considered a killer or yield limiting defect.

We depend, or hope to depend, on machines, especially computers, to do many things, from organizing our photos to parking our cars. Machines are becoming less and less “mechanical” and more and more “intelligent.” Machine learning has become a familiar phrase to many people in advanced manufacturing. The next natural question people may ask is: How do machines learn?

Recognizing diverse objects is a clear indicator of intelligence. Specific to semiconductors, recognizing various types of defects and categorizing them is an important task that initially was carried out solely by humans. Gradually, this classification process was automated by using computer programs running ever-evolving algorithms. Today, most defects are detected and classified by such systems in advanced facilities.

Before machine learning was widely used, there was a period when system set-up was done purely by humans. After learning about situations for a task through observation and experiments, engineers made rules and implemented them as programs for computers to run. In this implementation scenario, the machine does not learn, it just keeps repeating the process programmed, making decisions based on the embedded rules. This is a very labor-intensive approach—to extract the rules from human classifiers, create the programmatic logic to implement these rules, and to verify the result. Sometimes it’s very difficult, or impossible, to translate a decision-making process that humans do, often subconsciously, into computer language.

The multiple demands of 3D NAND to enable yield and performance increase in difficulty at each generation. First generation devices, at 24-32 layer pairs, pushed process tools to extremes, going quickly from 10:1 to 40:1 aspect ratios for today’s 64-96 pair single tier devices. The aspect ratios increased as fast as the manufacturing challenges. To continue bit density scaling, processing improved to enable multi bit storage per layer, but still even more layer pairs are needed. With increasing layer pairs, plasma etch becomes exponentially slower.

This was quickly addressed by tier stacking—splitting the massive stack into two tiers—and it will likely increase to three or more tiers in the future. The advantage of a two-tier process is that it reduces the single etch step to a more manageable process, i.e., two 64 pair etches instead of one 128, or two 96 pair instead of one 192. 256 pair, two or three tier devices, are in development now, and 384 or more expected soon. The channel hole control improved in terms of individual profile, but at the cost of increasing device integration challenges, like adding a joint into the middle of the stack. These integration challenges are confounded by combining variation from multiple process steps. There is an increasing need to identify, measure, separate, and control each of these sources of variability.