If you’ve been following the evolution of advanced packaging, you know that the industry is pushing boundaries like never before. From high-performance computing to industry-upending AI devices, the demand for smaller, faster, and more powerful chips is driving innovation at every level. One of the unsung heroes in this transformation: Glass carriers.
These carriers are becoming essential for applications involving high-bandwidth memory (HBM), 2.5D/3D integration, and chiplet architectures. During the manufacturing process, glass carriers serve as mechanical support for thin wafers and panel-level packages. Why? Glass carriers are noted for their warpage resistance, superior rigidity, and thermal stability. This combination of glass’ exceptional flatness and rigidity enables the precise placement of dies and interposers. Additionally, glass is optically transparent, which allows through-glass alignment during bonding and stacking, a critical capability for 3D integration where multiple layers must be accurately registered.
The benefits of glass carriers, however, come with several challenges, none of which should come as a surprise to anyone who has ever handled glass, whether in the fab or at home. Glass is fragile and, as such, is prone to surface defects, subsurface inclusions, and residual stress. Each of these can negatively impact die attachment quality, interconnect reliability, and die yield.
Let’s take a look at three major yield-killing culprits.
Surface defects such as particles, pits, and scratches are among the most common issues and may occur during glass carrier handling and processing, compromising the structural integrity and performance of advanced packaging assemblies (Figure 1). Particles can interfere with the bonding process, leading to poor adhesion or electrical discontinuities, while pits and scratches can propagate stress points that weaken the carrier during thermal cycling or molding.
However, subsurface inclusions and organic contamination, which are often introduced during reclaim or cleaning, pose more critical challenges. Inclusions within the glass can create localized stress concentrations, while organic residues can reduce UV transmission and cause bonding failures. These contaminants are particularly problematic in high-density interconnect environments where optical clarity and surface purity are critical.
Figure 1: Common glass carrier defects
In addition to surface and subsurface defects, residual stress represents a concern. Over time, these stress points, manifesting during thermal processing or mechanical handling, can lead to cracks or delamination, undermining the thermo-mechanical integrity of the entire package.
These potential challenges are compounded each time a glass carrier is reused in an effort to reduce overall packaging costs. Fortunately, technologies have been developed to address this obstacle. These technologies integrate AI-driven defect classification, real-time analytics, and adaptive scanning modes to maintain throughput without sacrificing accuracy, enabling manufacturers to detect surface anomalies, subsurface inclusions, and stress-induced defects with unprecedented precision.
Enabling Defect-Free Glass Carriers
Today’s wafer-based inspection platforms utilize laser scatterometry and imaging techniques to inspect for nanometer sized defects on a variety of opaque and transparent/semi-transparent substrates. These substrates may be suitable for either R&D or high-volume advanced IC substrate (AICS) and fan-out panel level processing (FOPLP) environments. Proprietary inspection technology with multiple detection channels and advanced signal processing algorithms is applied to achieve accuracy and reliability in glass carrier inspection.
Figure 2: Results of top (blue) and bottom (red) defect mapping.
With each channel optimized to capture unique scattering and reflection signatures, the technology differentiates between surface and subsurface defects, as well as stress-related anomalies, with remarkable accuracy. Surface particles, scratches, pits, bumps, surface contamination, film or bulk wafer stress, voids/inclusions can be detected, measured, characterized, and imaged. One of the most significant capabilities of this technology is the ability to conduct simultaneous top, bottom, and internal defect mapping, a critical need for transparent and semi-transparent substrates where defects can occur across multiple planes (Figure 2).
Beyond defect detection, Angstrom-level film thickness measurement provides precise control over surface coatings and residual layers. This capability is particularly valuable in the glass reclaim process where even minor variations in film thickness can impact UV transmission and bonding performance. By enabling accurate defect detection and grading, only glass carriers meeting stringent quality standards are returned to production.
By introducing technologies that mitigate risks by providing comprehensive defect mapping and stress analysis, manufacturers are able to maintain the mechanical and thermal integrity required for next-generation devices. This capability is especially valuable in markets such as AI devices, high-performance computing, and automotive electronics where reliability is non-negotiable. With this combination of advanced optical technology and robust algorithmic analysis, manufacturers can successfully achieve higher yields, lower costs, and greater confidence in their packaging processes.
Conclusion
As packaging complexity grows and the use of glass carriers increases, inspection systems that combine multi-depth defect mapping and stress analysis will become indispensable for ensuring yield and reliability in AI and HPC devices. With the explosive growth in AI-driven data centers and advanced packaging architectures, manufacturers need solutions that combine accuracy, speed, and cost efficiency. The laser-based wafer inspection technology discussed in this blog meets several glass carrier challenges head-on while enabling advanced packaging houses to maintain defect-free glass carriers in support of next-generation advanced packaging.
The future of glass carriers is clear: with the right technologies at the ready, manufacturers have the tools and the means to meet the growing needs of the AI and HPC markets.
Biography
Jason Lin is Director of Product Marketing at Onto Innovation.
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AI workloads are pushing the boundaries of compute, memory, and interconnect architectures, and to meet these goals, manufacturers are rapidly accelerating advanced logic and DRAM development. Chief among these innovations: gate-all-around (GAA) logic transistor and vertical gate (VG) DRAM, two device architectures that promise higher performance, improved power efficiency, and greater scalability.
However, the arrival of these device architectures introduces new levels of manufacturing complexity brought on by increasing high aspect ratios (HAR) and the continued shrinking of device dimensions by roughly 20–30% per generation. Fortunately, new capabilities in optical critical dimension (OCD) metrology are up to the challenge of measuring and monitoring features, such as gate profiles, film thickness, and structural uniformity, at the nanometer scale. With the right tools on hand, manufacturers can maintain high volume process control for GAA logic and VG DRAM in the AI era (Figure 1).
Figure 1: GAA (left) and vertical gate DRAM (right) present new challenges for process control (pictured above)
These new capabilities are enabling the delivery of accurate, high throughput measurements across complex 3D geometries like GAA and VG DRAM by offering smaller spot size, higher signal sensitivity, and enhanced precision.
But before we discuss these new capabilities, let’s dive deeper into the challenges of both device architectures. We’ll start with GAA.
Challenges and Solutions
GAA transistors feature HAR channels and stacks of multi-layered nanosheets, in some cases as thin as 10nm. The manufacturing complexity lies in controlling individual nanowires and accurately characterizing buried nanowires within three-dimensional architectures. Precise control over nanowire dimensions is critical for achieving the desired electrical performance, including higher transistor speeds and lower power consumption. As such, GAA manufacturers need metrology solutions capable of extracting unique signals with high sensitivity and precision from each layer, even those deeply buried under semi-opaque stacks.
While GAA logic presents unique challenges in transistor scaling, VG DRAM introduces equally complex demands in memory architecture. VG DRAM involves vertical nanowire etch, multi-layer ultra-thin film deposition, sidewall trim, and buried bitlines, electrical connections that are embedded deep within the silicon substrate rather than being placed on the surface, helping reduce the footprint of each memory cell. Additionally, VG DRAM for HBM4 features smaller cell blocks. Addressing these challenges requires an OCD system with a significantly smaller spot size in order to conduct direct on-device measurements. This, unfortunately, reduces the signal strength of optical systems.
For both GAA logic and VG DRAM devices, incorporating real-time stabilization technologies and advanced optical modeling can improve measurement precision and enable tighter process windows. In addition, AI-guided analysis allows fabs to create robust measurement recipes faster and with greater accuracy for highly complex device structures like nanosheets and VG DRAM cells. Analysis software also enables more accurate measurements that are scalable across multiple tools, while supporting smart manufacturing and predictive analytics for advanced AI applications.
Many of today’s OCD metrology tools, however, have limited SNR to measure these increasingly smaller changes in the complex device structure, while other systems do not have sufficient information to separate signals from multiple parameters (e.g., dimensions from individual nanowires) in complex device structures. Furthermore, most OCD metrology systems feature large spot sizes that do not fit into the reduced DRAM cell block area for HBM4.
Without the proper advanced metrology solutions addressing these challenges, manufacturers risk variability in critical dimensions and compromising device performance and yield. As such, more data channels and enhanced SNR at higher speed are needed to overcome the reduced signal strength due to smaller geometries and increased signal complexity from higher nanowire stacks.
Onto Innovation has recently added a number of optical and algorithm innovations to its OCD arsenal, such as new multi-polarization angle data channels with real-time stabilization technologies to enhance information content and SNR. These new capabilities offer advanced optical modeling, improving measurement precision, and robustness. Furthermore, the addition of AI-guided analysis software allows fabs to create robust measurement recipes faster and with greater accuracy for highly complex device structures. This includes nanosheets and VG DRAM cells. The use of analytical software also enables more accurate measurements and is scalable across multiple tools, all in support of smart manufacturing and predictive analytics for advanced AI applications.
Conclusion
As the semiconductor industry advances toward AI-optimized architectures, the need for more precise and adaptive process control has become critical. The new OCD capabilities discussed in this blog enable tighter control over individual nanowires in GAA logic and allow for more accurate measurements within increasingly compact VG DRAM cell blocks. Combined, these innovations represent a foundational shift in how the industry measures, monitors, and optimizes the most advanced semiconductor technologies.
Jiangtao Hu is a product marketing senior director at Onto Innovation.
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The demand for high bandwidth memory (HBM) is accelerating across the semiconductor industry, driven by boundary-pushing artificial intelligence, high-performance computing, and advanced graphics. These technologies require access to vast datasets, which in turn increases the need for memory solutions that combine speed, density, and power efficiency. HBM meets these demands by vertically stacking memory dies and linking them with ultra-fast interconnects.
With data rates rising, the need for increased output contact pad density is needed. To address this, bump technologies are being pushed beyond what was previously thought to be their physical and performance limits. As it stands today, some memory designers are innovating their way to bump sizes below 10µm in high volume manufacturing. Be that as may, scaling bump height to 2μm will be considerably challenging, leading some to explore hybrid bonding as an interconnect solution.
Hybrid bonding enables finer interconnect pitches of less than 10μm, allowing for more I/O terminals in a smaller area. This increased density translates directly into higher bandwidth and improved overall performance.
Traditional bump-based stacking introduces gaps of about 30μm between dies, while hybrid bonding offers direct Cu-to-Cu connections. By achieving near-zero spacing between dies, hybrid bonding significantly reduces overall package thickness and offers lower resistance and better thermal conductivity than bump-based methods. The result: improved signal integrity, reduced power consumption, and enhanced heat dissipation, each of which are critical for HBM.
Finally, hybrid bonding supports several configurations: wafer-to-wafer, die-to-wafer, and die-to-die, offering flexibility in manufacturing and integration. This adaptability is vital for scaling HBM technologies across different applications and performance tiers.
Of course, hybrid bonding offers manufacturers its own set of challenges—increased sensitivity to particles and organic residues, lower yields and introduction of more costly process and process control steps—making the decision to stick to the tried-and-true microbump technology over the emerging, innovation a debate worth having.
In this two-part blog series, we will compare these two interconnect solutions and discuss the challenges they face (Figure 1).
Figure 1: Interconnect challenges in microbump and hybrid bonding technologies.
Head to Head: Microbumps and Hybrid Bonding
Bumps have several advantages over hybrid bonding. As a mature technology, they are widely used and well-understood in the industry. They are also compatible with existing flip-chip and underfill processes, and are scalable for moderate density. In addition, the cost of bump technologies is lower than hybrid bonding technologies.
However, microbumps have a number of disadvantages compared to hybrid bonding. The most significant of which are the pitch limitations of bump technologies. Microbumps struggle at pitches below 10µm due to challenges in plating uniformity and solder reflow. Bumps also require underfill, which can introduce stress and complicate thermal management.
Limitations aside, bump technology continues to evolve. Leading suppliers of bump plating systems project a continued downscaling of bump dimensions, with diameters decreasing to the 5µm to 4µm range and heights dropping as low as 2µm to 1µm. At a 10µm pitch, the lateral footprint remains sufficient to support the high-density I/O requirements of advanced memory architectures. Concurrently, the reduced bump height enables vertical integration of up to 16 stacked HBM dies within the 775µm maximum package height defined by Joint Electron Device Engineering Council (JEDEC) standards. Consequently, bump interconnects remain a viable and scalable solution for next-generation HBM, and major manufacturers are maintaining substantial R&D investments in bump technology.
Hybrid bonding, while promising, presents its own set of challenges. Chief among them, hybrid bonding is especially sensitive to particles and organic residues; for example, even 1µm particles can cause defects. These residues can prevent proper contact, trap gases or moisture, and lead to void formation during bonding. Voids can cause delamination or incomplete bonding, reducing mechanical integrity and electrical continuity. Hybrid bonding also is more expensive than traditional bump technologies and may require manufacturers to purchase new equipment and adopt new process flows before moving away from bump technology.
Conclusion
As demand for HBM intensifies, the industry stands at a crossroads in interconnect technology. While microbumps have evolved to support increasingly dense and tall HBM stacks, they face several obstacles. Hybrid bonding offers a compelling alternative, but not without its own hurdles. Ultimately, both technologies are advancing in parallel, each with unique strengths and limitations.
Regardless of which interconnect technology is chosen, a comprehensive suite of interconnect solutions will be needed to address the obstacles manufacturers of HBM devices face. In the second in this two-part series, we will explore a number of these solutions that, when combined, tackle the biggest challenges facing interconnects in HBM.
Biography
Damon Tsai joined Onto Innovation in 2018 and has extensive experience in inspection and metrology, with a specialized focus on semiconductor FEOL, advanced packaging, OSAT, and specialty markets like RF, Power, and CIS. He currently serves as the Senior Director of Product Marketing, Inspection.
Woo Young Han joined Onto Innovation in 2000 and is currently Product Marketing Director, Inspection. He holds an Electrical Engineering degree from University of Toronto.
Tim Kryman is Product Marketing Senior Director, Metrology and Inspection. Tim has been with Onto Innovation for more than 20 years and holds a BS in Accounting and Information Systems from Lock Haven University and an MBA from DeSales University.
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At some point in our lives, we have dropped a drinking glass or knocked over a glass-blown knickknack, only to watch it hit the floor and shatter into pieces. We learn from any early age that glass is fragile. But if glass is so fragile, why are manufacturers adopting glass core substrates?
Good question. And one that comes with a ready answer.
Glass is able to meet the new, denser line-space specifications—1.5µm and below—for interconnects that advanced logic nodes and advanced packages require. Two, glass core is better suited for large package sizes than organic substrates (Figure 1). And contrary to what those outside the semiconductor industry may think, glass substrate offers superior mechanical strength compared to its organic counterpart.
As it stands today, organic substrates will remain viable for advanced packages, but in the near future glass substrates might emerge as the preferred substrate for high-performance applications (Figure 1).
Figure 1: Roadmap for organic and glass core substrates
Through glass vias (TGVs) are the critical vertical electrical connections that pass through a glass substrate, and they require ultra-precise processing. Unfortunately, each step opens the process to a host of potential defects. Cracks, in particular, are problematic. A small crack early in the process has the potential to grow into a much larger, “killer” defect later in the manufacturing process that affects the performance and reliability of the end product.
These challenges are not limited to cracks, however. The position accuracy of TGVs is vital to ensure reliable electrical connections between the front and back of the glass substrate. Even slight misalignments can lead to signal integrity issues or device failure. In addition, the shape and size of the vias are another area of concern; as a result, the critical dimensions (CD) of these vias must be tightly controlled. The relationship between the top, bottom, and waist diameters of a TGV determines the taper angle and profile of the via. If the sidewall is too steep or reentrant (narrower at the bottom), it can affect the plating process, leading to incomplete metal-filled vias or voids, impacting the electrical signal performance and reliability of the final device.
As glass core substrates are growing in adoption, the TGV process is being rapidly developed, with process control challenges spanning the entire process. Proper process control includes ensuring the cleanliness of the incoming bare glass, determining the thickness uniformity of the glass, and measuring critical dimensions after each process step, from laser modification and chemical etching to metal filling. Control for each of these is critical to maintaining the integrity of the final product and optimizing yields.
In this blog we will explore how a combination of metrology and inspection tools, along with software analytics, can be used to help develop TGVs, beginning with the inspection of the bare glass, continuing with measuring the thickness of the glass, and following with measuring the CD of the vias themselves.
Bare Glass, Glass Thickness, and Critical Dimensions
Before the TGV fabrication process even starts, it is important make sure the glass panel is free of defects (Figure 2). After all, you do not want to start off with a panel that already has an inclusion defect or crack. By using laser-based scanning and imaging optics and sensing technologies, manufacturers can reliably inspect bare glass for nanometer-sized defects, like particles, scratches, pits, and stains.
Figure 2: Glass panel with TGV.
It is also necessary to measure the thickness of the glass before starting the TGV process. Thickness uniformity across the glass panel is key. Consider this example: let us say that the thickness of a glass panel is 400µm at one end of the panel and 300µm at the other end. While this is an extreme example, you can imagine the effect that this might have on TGV height across the panel and the disastrous effect it would have on the performance of any device made from this glass substrate.
While inspecting the glass and measuring glass thickness before manufacturing begins is of considerable importance, there are a number of specific process steps throughout the TGV fabrication and metallization process where CD metrology and defect inspection are vital.
After the laser modification and etching process, manufacturers need to measure CD at the top of the via, the waist of the via, and bottom of the via;. A high-resolution, high-throughput optical panel inspection and metrology system can be used to measure these parameters for every single TGV on the panel, enabling precise monitoring of the etching process. In addition, the ability to detect defects such as incomplete etching, microcracks along individual TGV, larger cracks between multiple TGVs, and dimples and dents on the glass surface are crucial for process optimization.
In the metallization and planarization step, inspection systems can continue to monitor for defects such as residues, over/under plating, excess/insufficient polishing, and surface roughness, each of which could affect the overall electrical performance.
With millions of TGV on a panel, the ability to analyze a large quantity of inspection and metrology data within a short time period is a significant capability. The use of yield management software can shorten the time for analysis, identify systematic defects, and correlate process parameters with yield outcomes.
Conclusion
The adoption of glass core for IC substrate is currently at the starting point of what could be considerable market growth. By 2030 glass core substrate revenue is projected to grow to $275 million, according to best case scenario results from the . With the right tools on hand, manufacturers will be equipped to meet the rising demand for glass core substrates.
However, unlocking the full potential of glass core substrates and TGVs are not just about having tools; it is about using them in concert to build a process that is robust, repeatable, and yield optimized. As the adoption of glass as a substrate accelerates, manufacturers that invest in comprehensive process insight will be the ones that lead.
Monita Pau is Strategic and Product Marketing Director, Advanced Packaging, at Onto Innovation.
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Heterogeneous integration is a key enabler of today’s AI innovations. By bringing together multiple chips with different functionalities, a.k.a., chiplets, AI devices have been able to achieve tremendous performance gains. However, the heterogeneous integration of advanced packages has its own set of process control obstacles that must be addressed, including new interconnect challenges involving redistribution layers (RDL) and bond pads.
Recently, Onto Innovation and Samsung Electronics Co., Ltd., teamed up to explore how picosecond ultrasonic technology could be used to measure the metal thickness of RDL and bond pads in high performance AI packages. In this blog, the second in our series on the advanced packaging applications of picosecond ultrasonic technology, we will show how this technology can be used to measure metal films during RDL and bond pad processes.
But first, a word about picosecond ultrasonic technology, a widely adopted non-contact, non-destructive acoustic technique that can be used to measure film thickness.
Measuring Films
Picosecond ultrasonic technology measures film thickness by tracking the round-trip travel time of ultrasonic waves generated and detected using an ultrafast laser pump probe technique. A short laser pulse (pump) creates an acoustic wave that travels through the film, reflects at material interfaces, and returns to the surface. A second laser pulse (probe) detects the returning wave.
Two detection methods can be used to determine film thickness or properties:
- REF mode senses changes in surface reflectivity caused by the returning wave.
- PSD mode detects surface deformation by measuring shifts in the reflected probe beam.
By measuring the time it takes for the wave to return and knowing the speed of sound in the material, the film thickness can be accurately determined to sub-angstrom levels.
This level of layer-specific metrology, precision, and measurement repeatability is increasingly critical as AI-driven packaging pushes the limits of interconnect density and uniformity.
Accuracy and Repeatability
For the purpose of our exploration, we conducted a test to confirm the accuracy of picosecond ultrasonic technology when measuring the films typically used in advanced packaging. These metals include Au, Ni, physical vapor deposition (PVD) seed Cu, and RDL Cu (EP). For each film we used picosecond ultrasonic technology to measure wafers of varying thicknesses. Then we cut the wafers for cross-section analysis and estimated the correlation with the picosecond ultrasonic results for the four films (Figure 1). In this scenario, the correlation factor R2 was higher than 0.99 for all four cases, with the slope close to one, demonstrating the accuracy of picosecond ultrasonic measurements.
This level of correlation is not only impressive, it is essential. Competing technologies such as four-point probe (4PP) or contact profilometry often fall short in multilayer structures or non-planar surfaces, where mechanical contact can distort results or damage delicate features.
Following this, we measured product wafers in various interconnect processes with picosecond ultrasonic technology, including seed Cu/Ti measured in REF mode (Figure 2) and RDL in PSD mode (Figure 3). RDL thickness can be measured both in pre- and post-seed Cu removal.
The horizontal axis in Figures 2 and 3 represents the time delay of the probe pulse with respect to the pump, while the vertical axis represents the change of reflectivity (ΔR/R) caused by the travelling acoustic wave. The sharp change of reflectivity in the signal, as demonstrated in Figures 2 and 3, is mostly due to the acoustic wave reflected from the film interface returning to the surface. In addition, the position of the peak and trough is shown with red arrows. These arrows are directly related to the thickness of the films, seed Cu, barrier Ti, and EP Cu. From the position of the peak and trough, the thickness of each film can be calculated. For seed Cu and barrier Ti, the repeatability of each layer is 0.3% or less of the thickness for all measurements. This demonstrates the capability of picosecond ultrasonic technology to meet 10% gage repeatability and reproducibility requirements.
For RDL Cu, the sharp change of reflectivity near 2,200 picoseconds (ps) corresponds to the round-trip time of the acoustic wave within the RDL Cu film; Cu thickness can be calculated from the trough position. The sharpness of the trough, along with thickness, indicates the trough position can be calculated with good repeatability. In fact, the repeatability of RDL Cu measurements for each point is less than 0.1% of Cu thickness, once again exceeding the 10% gage repeatability and reproducibility requirements.
Such precision is a necessary technical achievement. As AI applications demand tighter control over signal integrity and power efficiency, the margin for error in interconnect thickness shrinks dramatically. Legacy tools simply cannot keep up.
Measuring Bond Pads with Dimple Structures
We also used picosecond ultrasonic technology to measure a bond pad with a dimple structure. The film stack is composed of Au/Ni/Cu, with Au being the top film. Although the height of the center region of the pad is lower than the surrounding region by a few microns, we successfully measured individual layer thicknesses by measuring a few sites in the outer ring area and selectively choosing ones with good signal-to-noise ratios. This is possible because the focused spot size of the picosecond ultrasonic beam is 8×10µm2, small enough for the direct measurement on the outer ring of the pad.
This is another area where contact-based methods struggle. The ability to selectively target small, non-planar regions without physical interference is a key differentiator of picosecond ultrasonic technology.
In Fig. 4 a-b, the red arrows indicate the reflectivity changes caused by the acoustic waves returning from the interface to the surface. With these peak positions, we were able to calculate each layer’s thickness with good accuracy and repeatability. The repeatability of Au, Ni and Cu films for each measurement was less than 0.2%, 0.05% and 0.05%, respectively. As such, all three film measurements outperformed the requirement of 10% gage repeatability and reproducibility.
It should be noted that Au film is much thinner than the other two films. As such, there is a significantly higher repeatability for Au films compared with the other films.
Conclusion
The AI era is upon us, and it would not be possible without advanced packaging innovations. However, the complexity of today’s advanced packaging is worlds away from traditional packaging. Today’s back-end process involves a variety of technologies and requires new methods of process control. In addition, controlling metal thickness and within wafer uniformity in these processes is critical to meeting the requirements for signal integrity in advanced packaging.
Unfortunately, some fabs still rely on legacy metrology tools like 4PP or contact profilometry—technologies that were never designed for the complexity of modern AI packages. These tools often introduce mechanical stress, lack the resolution to resolve thin or buried layers, and cannot reliably measure non-planar or dimpled structures.
As we have demonstrated, picosecond ultrasonic technology is an ideally suited interconnect metrology solution for both RDL and bond pads. This technology offers excellent accuracy and gage capability for the control of interconnect processes in advanced packaging.
As back-end processes demand the same level of precision, uniformity, and control traditionally associated with front-end requirements, picosecond ultrasonic technology can play a major role in advanced packaging metrology, delivering the non-contact, high-resolution, and repeatable measurements that AI applications demand.
Acknowledgments
We would like to thank Dae-Seo Park, Sanghyun Bae, Junghwan Kim, and Hwanpil Park of Samsung Electronics Co., Ltd., and Kwansoon Park, G. Andrew Antonelli, Robin Mair, Johnny Dai, Manjusha Mehendale and Priya Mukundhan of Onto Innovation for their contributions to this article.
About the author
Cheolkyu Kim, Ph.D., is director of product marketing at Onto Innovation with a focus on application development for picosecond ultrasonic (PULSE™) and inspection technologies. Prior to joining Onto, Kim was a postdoctoral research associate in the Physics Department of Brown University. During his three years at Brown, he spent time researching magnetically levitated superfluid liquid helium.
If you are a part of the semiconductor industry or simply someone interested in the field, you have likely heard what has become a common refrain: the back-end of the process is becoming more like the front-end of the process. In other words, the technologies that were once exclusively deployed in the first part of the process are being used to meet the increasingly stringent requirements of advanced packaging on the back of the process.
This is especially true for complex AI devices, where heterogenous integration brings together multiple chips with different functionalities. These devices present manufacturers with new interconnect challenges, especially when it concerns redistribution layers (RDL) and bond pads. This is certainly the case for high-bandwidth memory chips, some of which may feature eight to 12 interconnected DRAM chips. And those numbers are only going to climb higher, while the need to properly measure interconnects is only going to grow in importance.
With RDL and bond pad metrology, the need to measure sites under 10μm is emerging as a new requirement. Unfortunately, traditional back-end approaches – like X-ray fluorescence or sheet resistance measurements and white light scanning interferometers – have limited capabilities that make them poor candidates for advanced interconnect process control. Measuring RDL and bond pads in AI packages requires traditional front-end metrology tools offering in-line process control capable of measuring small sites within a tight process control window (Figure 1).
The semiconductor industry has long adopted picosecond ultrasonic technology as a non-contact, non-destructive technique capable of providing accurate measurements for single-layer and multi-layer metal films. Recently, Onto Innovation and Samsung Electronics Co., Ltd., teamed up to explore how this front-end mainstay also could be used to measure metal thickness in RDL and bond pads in high performance AI packages.
In part one of this two-part blog series, we will focus on traditional techniques and current challenges, whereas in the second blog we will discuss solutions involving picosecond ultrasonic technology. But first, a quick word about the latest generation of picosecond ultrasonic technology.
Picosecond Ultrasonic Technology
In our study, we used fifth generation picosecond ultrasonic technology to measure the thickness of individual metals on multi-layer structures. To measure very rough film, pump beam intensity was modulated at 5 MHz. This modulates the intensity of the acoustic wave it generates. Then the reflected probe beam signal from the detector was demodulated with the same frequency as the pump modulation, allowing for the measurement of weak reflectivity changes caused by the acoustic wave.
As the pump beam itself does not convey any information about the travelling acoustic wave but has the same frequency as demodulation, demodulating the signal from the detector may include the signal from the pump, resulting in significant noise. This is especially the case when measuring rough films where pump beam scattering is strong. To address this, such noise can be filtered out by modulating the probe beam at a different frequency, 0.5MHz, and demodulating the signal from the detector with the sum of the two frequencies, 5.5 MHz.
Another significant improvement made to this technology is that the maximum probe beam time delay for the measurement has increased from 5 nanoseconds (ns) to 15ns. This means the maximum thickness that can be measured has increased threefold. For Cu measurement, the maximum thickness that can be measured is now 35μm.
With our discussion of picosecond ultrasonic technology out of the way, we will turn our attention to the advanced packaging needs of AI devices.
AI Packages
To create AI devices, manufacturers use heterogeneous integration to package memory and process chips together in 2.5 and 3D structures. This enables faster communication and lower power consumption.
In these structures, conventional memory chips are replaced with high bandwidth memory (HBM) and paired with a graphics processing unit (GPU). HBM enables the higher data transfer rates needed to handle the significantly increased data processing generated by parallel computation with the GPU. In the latest generation HBM, eight to 12 DRAM chips are connected to each other vertically by through silicon vias (TSV) to form one HBM package. Then four to six HBM packages are connected, horizontally, with the GPU chip by RDL on a Si interposer. These new interconnected structures offer significantly improved computing power and latency and higher bandwidth for data transfer and low power consumption. Each are needed for AI computing.
In the case of RDL on a Si interposer, manufacturing multiple layers of RDL is required to handle high data transfer rates. As such, the manufacturing process is more complex compared to the manufacturing process for mature packages.
Metals, mostly Cu, in RDL are typically deposited using the electroplating (EP) process. The thickness of the metals is affected by the geometric structure underneath, making thickness uniformity control very challenging. To meet the within wafer uniformity requirement for RDL impedance control, measuring and monitoring metal thickness directly on product wafers is crucial. As RDL lines shrink to 2µm or lower – the line/space (L/S) requirements of the most advanced packages – dimensional control is vital to device performance while process control itself becomes even more stringent.
After the final RDL layer on a Si interposer is formed, bonding pads are created. These bonding pads connect with HBM or GPU chips through micro-bumps. Like RDL, bonding pads are also created using the EP process. However, some bonding pads are flat while others possess a dimpled structure (Figure 2). To maintain process control, engineers will still need to measure metal thickness directly on both flat and dimpled structures. In the case of the latter, such measurements are a lot more challenging.
Traditional Packaging Process
During the traditional packaging process, metal film measurements are characterized using automated and semi-automated measurement tools such as X-ray fluorescence or sheet resistance measurements. While these tools are easy to use and offer low cost of ownership, they are not up to the task of measuring multi-layered films or films with varying topographies on product wafers in high volume manufacturing.
White light scanning interferometer (WLSI) systems are also used in RDL process monitoring. These methods rely on wavelength-dependent interference patterns to provide the step height of metals; this assumes that the step height is the same as metal thickness, which may or may not be true depending on the structure.
As RDL films become thinner, wavelength dependent interference patterns become less sensitive to thickness variation. This affects measurement accuracy. In the case of RDL lines 2µm L/S and lower, the accuracy of thickness measurements becomes even more critical for process monitoring and control. However, WLSI systems have shown limitations in meeting these metrology requirements.
In general, the front-end process must operate inside a window that varies within 10% of the target value. This, in turn, requires a metrology tool with a gage capability (3σ repeatability and reproducibility) of 10% of the variability or 1% of the target value. This metrology tool must be able to measure in-die areas and on test structures smaller than 50µm on real product wafers. Such a tool also needs to be non-contact, non-destructive and fast enough to support high volume production. Picosecond ultrasonic technology enables advanced packaging manufacturers to meet these challenges.
In our next blog, we will take a deep dive into how picosecond ultrasonic technology can be used to measure metal films during RDL and bond pad processes. We hope you join us as we continue to explore the advanced packaging applications of picosecond ultrasonic technology.
Acknowledgments
We would like to thank Dae-Seo Park, Sanghyun Bae, Junghwan Kim, and Hwanpil Park of Samsung Electronics Co., Ltd., and Kwansoon Park, G. Andrew Antonelli, Robin Mair, Johnny Dai, Manjusha Mehendale and Priya Mukundhan of Onto Innovation for their contributions to this article.
About the Author
Cheolkyu Kim, Ph.D., is director of product marketing at Onto Innovation with a focus on application development for picosecond ultrasonic (PULSE™) and inspection technologies. Prior to joining Onto, Kim was a postdoctoral research associate in the Physics Department of Brown University. During his three years at Brown, he spent time researching magnetically levitated superfluid liquid helium.