From consumer products to industrial applications, augmented reality (AR)/mixed reality (MR) technology is one of the most innovative interactive technologies on the market today. By overlaying digital information onto the physical world, AR/MR technology improves how people see, understand, and interact with their environment in real time. The industrial applications alone are cause for celebration, whether this technology is being used for training, assembly, or troubleshooting.
Be that as it may, one of the most significant challenges facing AR/MR lies in manufacturing the photonic components that control how light is generated, diffracted, guided, and delivered to the human eye.
An AR display usually consists of a light engine and an optical combiner. The light engine serves as a display image source, while the combiner delivers the displayed images to the viewer’s eye and transmits environment light (Figure 1). Surface relief grating (SRG) waveguides play a role in these optical combiners by coupling display light into, expanding it within, and diffracting it out of a transparent substrate toward the eye of the intended viewer. This component must deliver precise diffraction behavior while remaining transparent, lightweight, and scalable for high-volume manufacturing (HVM).
Balancing optical performance and manufacturability, however, places significant demands on fabrication and process control. Faced with this obstacle, device makers require solutions capable of addressing any negative impacts to launch timelines, unit costs, and OEM qualification.
Figure 1. Diagram of SRG waveguide-based AR display.
In this article we will discuss ways SRG manufacturers can address these challenges with an integrated process control solution tailored for the HVM of SRG. The solution combines optical critical dimension (OCD) metrology for the critical parameters of SRG such as grating depth, slanted angle, and periods; picosecond ultrasonic technology for the metal film thickness measurement; image‑based overlay (IBO) for precise overlay control in HVM specialty devices; and an automated optical inspection for defects integrated throughout the entire manufacturing process.
With these tools combined in a closed‑loop process control strategy, manufacturers have a framework that enables the consistent manufacturing of full‑color SRG waveguides capable of meeting the stringent optical and mechanical requirements of next‑generation AR/MR devices.
Navigating the Ramp to HVM
By coupling light into and out of a transparent substrate through precisely engineered diffraction gratings, SRG waveguides can deliver wide field‑of‑view, high brightness, and compact form factors. Unfortunately, manufacturers of SRG waveguides must face a host of challenges arising from multi‑layer and often double‑sided fabrication, with sub‑100nm alignment tolerances across large‑area substrates, if they hope to transition to HVM. The impact of these challenges, however, only grows as the manufacturing process goes on, increasing yield variability and making it difficult for makers of SRG components to meet the requirements expected by tier-one AR/MR customers.
To begin with, let’s turn to grating geometry. Manufacturers must control for period, depth, and slanted angle to ensure diffraction efficiency and uniformity across the field. Additionally, makers of these components must maintain proper thickness uniformity to avoid phase errors and color shifts; as such, thin‑film processes like mask deposition and etching must maintain exceptional thickness uniformity. Third, manufacturers must also maintain overlay accuracy between lithography steps, and they must do so within a fraction of the design tolerance to preserve red, green, and blue (RGB) multi‑period grating registration and double‑sided alignment. Finally, defect control is essential in the manufacturing process. After all, particles, scratches, and etch anomalies can cause scattering, reduce optical efficiency, and degrade image quality. Not surprisingly, the manufacturing process features a number of consequential steps (Figure 2).
In many cases, the process begins with the deposition of a chromium (Cr) hard mask on a SiO₂ substrate, followed by spin coating a resist layer. For master fabrication, electron beam lithography or deep ultraviolet lithography is used to pattern the grating structure. The resist pattern is then transferred to the Cr layer using a dry etching process, after which the residual resist is removed, leaving the Cr layer to serve as an etching mask for reactive-ion beam etching (RIBE). During RIBE, ionized argon beams are directed toward the substrate at an oblique angle to form the slanted grating profile. Once the target etch depth is achieved, the Cr layer is removed by chemical wet etching.
For HVM, the fabricated master grating is replicated using nanoimprint lithography (NIL) production due to its low cost and high throughput. In this process, the master pattern is first transferred into a polymer film to form a soft working stamp, which is then used to imprint a high refractive index (RI) resist layer. After imprinting, the pattern in the high-RI resist retains the same orientation as the original NIL template.
Figure 2. Basic flow in the manufacturing process of the surface relief grating waveguide.
These manufacturing challenges—spanning nanoscale grating fidelity, thin-film uniformity, overlay accuracy, and defect control—are tightly coupled and cannot be addressed in isolation without compromising yield or optical performance. Achieving stable, HVM requires coordinated visibility into each step of the SRG process. As it stands, makers of waveguide components rely on isolated measurements that diagnose symptoms without revealing root causes. In contrast, an integrated, closed-loop approach connects thickness, CD, overlay, and defect data, allowing engineers to correct process drift before it impacts customer-visible performance. By applying integrated metal film metrology, OCD measurement, image-based overlay control, and advanced defect inspection to the process flow, manufacturers are able to establish control and consistent SRG waveguide manufacturing, improving yield during ramp and reducing qualification cycle times, an important win for manufacturers ramping up HVM.
Tackling Thickness Non-Uniformity
As part of this integrated process control framework, thickness uniformity is a critical variable to address. In SRG manufacturing, thickness and uniformity must be precisely measured and controlled as it directly impacts downstream etch behavior, grating geometry, and ultimately optical performance. Uncontrolled metal film thickness is a frequent root cause of profile distortion and yield loss in SRG waveguides. When combined with CD, overlay, and defect control, the ability to measure metal thickness enables full process visibility across SRG manufacturing.
After deposition, the hard mask must be thick enough to remain intact throughout the entire etching process without being prematurely etched through. However, excessive thickness can distort the etched sidewall profile. Moreover, non-uniform thickness across the wafer can lead to variations in etch depth and grating tilt angle. This degrades diffraction efficiency and wavefront quality.
Figure 3. Cr and Al spectra and measurement result mapping.
To measure thickness, makers of SRG components can use an inline metal film metrology tool with picosecond ultrasonic technology. This tool offers rapid and precise determination of Al/Cr thickness across different substrates, delivering within wafer uniformity characterization that facilitates the early identification of process deviations.
In our demonstrations, we used an inline metal film metrology tool to gather data. The metrology system can measure metal film thickness across the wafer and with repeatable, stable precision over time, making it suitable for tight process control in high-volume SRG waveguide manufacturing. In production demonstrations, the results showed high-precision metal film thickness measurements with strong wafer-level uniformity and repeatability across representative substrates and multilayer film stacks (Figure 3). In addition, the metal film metrology tool achieved outstanding dynamic and static stability, thereby ensuring compliance with the rigorous demands of advanced process control as shown in Table 1. This level of control offered by the inline metal film metrology tool directly reduces grating profile drift between lots, lowering rework rates and preventing late-stage optical fallout during customer acceptance testing.
| Film information | Wafer Uniformity | Repeatability（1σ） | |||
| Average | Stdev | 1 σ | Static | Dynamic | |
| Si/Al3000Å | 2676.7 | 53.4 | 2.00% | 0.03% | 0.01% |
| Glass/Resin5000Å/Al3000Å | 2706.8 | 52.2 | 1.93% | 0.10% | 0.04% |
| Si/Cr220Å | 215.1 | 3.6 | 1.66% | 0.04% | 0.00% |
| Glass/TiO2600Å/Cr220Å | 223.2 | 4.5 | 1.99% | 0.15% | 0.10% |
Table 1. Cr and Al wafer uniformity and repeatability.
Meeting Tight Design Tolerances with OCD Metrology
In the fabrication of SRG waveguides, optical performance is highly sensitive to nanometer scale variations in grating period, depth, sidewall angle, and fill factor. Manufacturers of these components must adhere to the extremely tight design tolerances required for target coupling efficiency, polarization control, and chromatic uniformity throughout the manufacturing process.
To accomplish this, manufacturers can deploy OCD metrology based on rigorous coupled wave analysis (RCWA) to continuously monitor grating depth, CD, and sidewall angle before optical deviations propagate downstream. In demonstrations, we used an OCD metrology system based on RCWA to decode light scattering signals and simultaneously extract grating parameters across the entire wafer. Two types of SRGs were targeted: blazed SRGs and binary SRGs. Binary SRGs use a two-level stepped profile for phase or polarization control, and blazed SRGs use a slanted or ramped profile to efficiently direct light into a preferred direction.
Using OCD metrology, measurements of key parameters showed excellent agreement with reference metrology in representative SRG structures, confirming the suitability of OCD metrology for process control in SRG manufacturing. This stability enables tighter process windows and allows manufacturers to run closer to design limits without sacrificing yield, a critical need in situations where OEM specifications leave little margin.
Figure 4 .(a) OCD mode of blazed SRGs, matching with reference and dynamic performance. (b) OCD mode of binary SRGs, matching with reference and dynamic performance.
Preserving Full-Color Performance Through Precise Overlay
For manufacturers, maintaining overlay accuracy between successive patterning steps is a critical determinant of optical performance. Even small misalignments can cause coupling efficiency loss, field-of-view distortion, polarization imbalance, and chromatic aberrations.
Although a single SRG is typically formed in one patterning step, waveguide processes often require multiple patterning steps or the integration of several functional gratings on the same substrate. Representative cases include separate in-coupling and out-coupling gratings, multiwavelength gratings for full color operation, where red, green, and blue gratings of different periods are overlaid in the same location via multiple lithography or multiple nanoimprint patterning steps performed on both sides of the substrate, and precise registration with other micro-optical structures. These scenarios have stringent requirements. As such, overlay control at the submicron level is needed to preserve designed optical characteristics. Meeting these stringent alignment requirements in SRG waveguide architectures necessitates precise, wafer-scale overlay metrology. IBO techniques provide component makers with the capability to directly measure and control cross-layer and double-sided alignment in transparent substrates.
Figure 5. Bar-in-bar (BIB) and overlay fingerprint.
For our demonstration we used IBO technology enabling cross-layer and double-sided alignment in transparent waveguide substrates by matching grating pattern features. Using a bar-in-bar (BIB) mark for full map overlay measurement, demonstration measurements showed that the system achieved a precision of 0.26nm (X) and 0.18nm (Y) at 3σ (Figure 5). The measured tool-induced shift (TIS) was -2.63nm (X) and -0.71nm (Y), with corresponding 3σ TIS values of 0.62nm and 0.81nm, respectively (Table 2). Based on the industry standard 3σ definition, the resulting total measurement uncertainty (TMU) was 0.83nm in the X direction and 0.92nm in the Y direction. These results demonstrate that the overlay platform delivers sub-nanometer overlay capability and provides sufficient margin for the alignment requirements of high precision, full-color SRG waveguide manufacturing. In addition, the system provides correction parameters that can be directly applied to the lithography tool to compensate for systematic overlay errors.
| RG X Avg (nm) | RG Y Avg (nm) | RG X 3S (nm) | RG Y 3S (nm) | TIS X Avg (nm) | TIS Y AVG (nm) | TIS 3σ X (nm) | TIS 3σ Y (nm) |
| -71.8 | 36.0 | 0.3 | 0.2 | -2.6 | -0.7 | 0.6 | 0.8 |
Table 2. Overlay measurement statistics.
Detecting Submicron Defects
Defect inspection is critical to the manufacturing of SRG waveguides. Due to the unique nanoscale periodic structures and the optical sensitivity of SRG waveguides, even minor defects can lead to reduced diffraction efficiency, increased stray light, image non-uniformity, and other issues. As a result, defect inspection should be integrated throughout the entire SRG manufacturing process. In the mass production of SRG waveguides using NIL, manufacturers are enabled to detect organic defects from the photo resist, cleaning chemical residues, and high index resin which would normally escape detection under conventional brightfield or darkfield illumination schemes. In HVM undetected submicron organic defects can propagate across replicated stamps, turning a localized issue into a systemic yield problem.
The automated defect inspection system we employed provides fast and reliable inspection for submicron defects and the option to accurately measure 2D and 3D metrology features. Equipped with multiple illumination technologies, the inspection system is capable of capturing organic defects at or below 1µm. Standard optical inspection struggles with features at this size, opening the door to defect contamination that would otherwise be invisible but detrimental.
The Continued Evolution of AR/MR Technology
With the advent of mass production and declining costs of SRG waveguides, the coming years are poised to mark a transformative phase for AR/MR technology. This article presents an approach for full process control for the HVM of SRG waveguides, encompassing metal film metrology, OCD measurements of grating parameters, overlay alignment verification, and defect inspection—spanning from incoming substrate qualification to the validation of the final product.
The process‑control challenges discussed in this article extend across a broad class of AR/MR optical architectures, diffractive and meta-optical devices, and other nano-patterned optics manufactured at scale. Beyond SRG waveguides, the same process-control capabilities extend across a wide range of optical and photonic manufacturing applications, including other AR/MR waveguide architectures such as volume holographic and multi-level diffractive waveguides, as well as diffractive optical elements and meta-optics that rely on sub-wavelength pattern fidelity and precise depth control. These applications overlap strongly with optical thin-film stacks and functional coatings, micro-display manufacturing, and advanced optical and silicon-photonics packaging, all of which demand tight control of CD, overlay, film uniformity, and defectivity to reach HVM.
For manufacturers evaluating their next waveguide ramp, the key question is no longer whether SRG waveguides can meet optical targets, but whether their process control strategy can meet OEM schedules, cost models, and yield expectations at the same time. With the right integration of tools on hand, they can.
Biography
Alex Hong is a Senior Field Application Engineer at Onto Innovation, specializing in metal film metrology for semiconductor manufacturing, with additional expertise in optical critical dimension (OCD) applications.
The author would like to thank the rest of the team who worked on this article, including Onto Innovation’s Huayuan Li, Charles Zhang, Yuhang Lin, and Johnny Mu, along with Xiongwei Wang and Chenglong Jia of Sunny Optical Oulai Micro-Nano Optics (Shanghai) Co., Ltd.
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Every day, consumers rely on an invisible network of specialty semiconductor devices without realizing it. The smartphone in your pocket is a good place to start. It knows when you rotate the screen thanks to MEMS sensors, and its camera delivers crisp images through advanced CMOS image sensors. Meanwhile, fast charging technology, wireless connectivity, facial recognition, and high-frequency communications all depend on specialty power devices, radio frequency (RF) filters, and photonic technologies working seamlessly behind the scenes.
However, success in every specialty device category hinges on advanced process control solutions capable of ensuring what matters most is tightly understood and controlled. This may be shape, thickness, uniformity, defects, or material properties. And it all must be done at low cost of ownership while maintaining the throughput needed for high-volume manufacturing (HVM). For device manufacturers, failure to meet requirements doesn’t just increase process complexity, it directly translates into longer ramps, missed customer commitments, and higher cost per device.
As we explored in the first two parts of this of our Specialty Surge series, these unsung heroes of modern electronics are rapidly scaling in complexity and volume, causing headaches for device manufacturers. In this final blog, we’ll turn our attention to the strategies manufacturers can employ to make that pain go away. From advanced metrology to inspection and data-rich feedback for process control, we’ll explore the capabilities enabling specialty devices to deliver the performance consumers expect at the scale manufacturers want.
Challenges Revisited
Before we go any further, let’s recap the challenges specialty device manufacturers face, separated by device type. We’ll begin with microelectromechanical systems, a.k.a. MEMS.
MEMS – MEMS include a variety of device types, including pressure sensors, gyroscopes, accelerometers, microphones, and surface acoustic wave (SAW)/bulk acoustic wave (BAW) radio frequency MEMS. These devices demand extremely tight control over specialized materials and fabrication steps, where small variations in film thickness, crystal orientation, and etch quality can directly degrade performance. Across MEMS, the core challenge involves maintaining wafer-level uniformity and precise feature profiles at scale to ensure consistent electrical, mechanical, and frequency behavior.
CMOS Image Sensors (CIS) – Modern CMOS image sensors are extremely sensitive to nanoscale process variation. As such, they require tight control of epitaxial thickness, dopant uniformity, and trench dimensions to achieve low noise and high light-capture efficiency. The challenge is amplified by the device’s stacked architecture, which demands precise metrology and inspection across pixels, CMOS circuitry, and microlens layers to maintain uniform performance.
SiC and GaN Power Devices – SiC and GaN power devices face growing manufacturing challenges with the use of 300mm wafers. These challenges include crystalline defects, epi thickness variation, CD control, and backside and particle defects, all of which can impact yield and reliability. The core challenge for manufacturers of power devices is to maintain rigorous inspection and metrology for thick, defect-prone wafers while keeping cost-of-ownership competitive with conventional silicon power devices. The inability to distinguish benign defects from true killer defects early in the process can result in unnecessary scrap, escaped reliability failures, or overly conservative screening that limits output.
Photonics and Co‑Packaged Optics (CPO) – Silicon photonics and co-packaged optics face significant manufacturing challenges due to the tight integration of lasers, waveguides, microlenses, and opto-electronic components within a single high-density module. Achieving reliable performance requires precise control of optical features, material uniformity, and multi-die assembly across multiple process domains where small variations can cascade into system-level loss.
Enabling Precision and Control in Specialty Device Manufacturing
Many of the challenges manufacturers face in the specialty segment can be addressed through capabilities integrated directly into the process flow. These capabilities enable real time adjustment and control of the fabrication process to maximize yields and improve device performance.
MEMS Devices – In RF BAW manufacturing, device performance is extremely sensitive to small variations in piezoelectric film thickness and acoustic stack uniformity. Traditionally, inline measurements help identify non-uniformity, but they do little to directly correct it. By combining high-precision, inline thickness metrology with software-driven run-to-run process control, manufacturers can move beyond passive monitoring to active performance control.
In this application, wafer-level thickness data are analyzed in real time to quantify across-wafer non-uniformity trends. That information is then fed directly into a downstream trimming process, where correction parameters are automatically adjusted on a wafer-by-wafer basis. The result is a closed-loop workflow that not only detects variation but actively compensates for it, reducing across-wafer non-uniformity by an order of magnitude. This integrated approach enables manufacturers to hit tight frequency specifications earlier in ramp, reduce binning losses, and improve RF BAW yield at production scale.
While this approach is specific to RF BAW devices, similar combinations of inline metrology and software-driven process control can be applied across other MEMS devices to stabilize critical dimensions, structural layer thickness, and structural symmetry that directly impact sensitivity, bias stability, and long‑term reliability.
CMOS Image Sensors (CIS) – Modern CIS are built on stacked architectures that combine pixel structures, CMOS circuitry, and optical elements such as microlenses. While individual inspection or metrology steps can highlight issues within a single layer, many yield and performance problems emerge only when variability compounds across the full stack.
To address this, manufacturers increasingly correlate inspection and metrology data across multiple layers of the CIS flow. Structural and defect inspection of isolation trenches, metrology of epitaxial thickness and dopant uniformity, and optical-layer inspection are combined through software to build a unified view of pixel formation. This cross-layer correlation allows engineers to trace image non-uniformity or noise back to its true origin, whether it begins in epitaxy, implantation, trench definition, or optical layers, rather than discovering the issue late in the flow. By unlocking this multi-layer insight, manufacturers can intervene earlier, preserve image quality, and protect yield across increasingly dense pixel arrays.
SiC and GaN Power Devices – Wide-bandgap power devices such as SiC and GaN introduce a unique challenge: crystalline defects originating in the substrate can propagate vertically through epitaxial layers, becoming latent or killer defects in finished devices. Identifying which defects truly matter requires more than isolated inspection. It demands full wafer visibility and data correlation across process steps.
Figure 1: 360° full wafer defect view including sub-surface defects. In this image, concentric circular fields represent the frontside, edge and bevel areas of the wafer.
In this application, manufacturers begin by capturing a 360-degree view of the wafer, inspecting the frontside, backside, and edges to fully characterize the defect population. Substrate inspection performed before epitaxial growth identifies crystal defects early, while post-epi inspection reveals which of those defects persist and propagate into active layers. Software then correlates defect maps across both stages to isolate defects that originate in the substrate and extend through the epitaxial stack.
To further distinguish benign defects from true killers, electrical characterization is applied at the substrate level to measure defect resistivity. Defects that both propagate vertically and exhibit low resistivity—an indication of a high likelihood of current leakage or shorting under operating conditions—are flagged as true killer defects. This multi-modal, correlated workflow transforms inspection from simple defect counting into root-cause analysis, enabling smarter screening decisions, higher yield, and improved long-term device reliability.
Photonics and Co-Packaged Optics (CPO) – Photonics and co-packaged optics (CPO) represent one of the most integration-dense manufacturing environments where independently fabricated components must ultimately function together as a single optical system. Defects that appear manageable at the component level can compound during assembly, leading to significant system-level optical loss.
At the component level, precision metrology and inspection are applied to each critical element. V-groove structures are measured for angle, depth, and height while simultaneously being inspected for particles or obstructions that compromise fiber alignment. Waveguides are analyzed for width, height, sidewall angle, and roughness, allowing manufacturers to correlate structural variation and local defects directly to optical loss. Microlenses are screened for deformation, cracks, or surface contamination that could degrade beam quality. Laser devices are monitored for mesa geometry and aperture dimensions, with feedback applied to etch processes, thereby stabilizing optical power and wavelength.
The challenge intensifies during final CPO assembly where multiple die are bonded, stacked, and aligned within a single module. Inspection at this stage must verify placement accuracy, bonding quality, and die planarity. Even minor warpage or misalignment can negate upstream process control. By integrating data from component-level inspection through final assembly, manufacturers gain visibility into compounding defect mechanisms and can intervene before system-level failures occur. In CPO manufacturing, this integrated approach is essential to protecting yield and optical performance.
Integrated Intelligence
Across MEMS, CIS, power, and photonic devices, specialty device manufacturers may find that the greatest value comes from integrating metrology and inspection data across tools, layers, and process steps. By correlating structural, optical, electrical, and defect information—often with 360-degree wafer visibility—manufacturers can move from reactive defect detection to proactive process control.
This integrated approach is critical to achieving the performance, yield, and reliability required for today’s most advanced and highly specialized semiconductor devices. Ultimately, manufacturers benefit most when inspection and metrology stop being isolated checkpoints and instead function as an integrated manufacturing intelligence layer that shortens ramp times, protects yield, and accelerates time to market. The challenge is no longer whether defects can be found, but whether insight can be gained early enough to act before yield, schedule, or reliability are impacted.
Christopher Haire is a marketing content specialist at Onto Innovation and a former business journalist.
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From the cars we drive to the devices we hold and the medical systems that safeguard our health, bipolar-CMOS-DMOS (BCD) technology is at the heart of many modern electronics.
Today’s vehicles are packed with electronics like power engine management, anti-lock braking systems (ABS), airbag controllers, and electric vehicle (EV) charging infrastructure, each one demanding a seamless integration of analog, digital, and power functions. In the case of smartphones, audio amplifiers, and smart home devices, BCD devices help balance power efficiency with high performance. Meanwhile, medical imaging systems, such as ultrasound, and advanced power management solutions, rely on semiconductor technologies like BCD devices to handle diverse electrical requirements without compromising accuracy or safety.
Important as BCD devices may be, what exactly are they?
BCD devices are an advanced semiconductor process technology that integrates three distinct types of transistors—bipolar, CMOS, and DMOS—onto a single chip. The integration of these three transistors enables the simultaneous handling of analog, digital, and power functions within a compact and high-performance platform, with each transistor type contributing unique strengths:
- Bipolar transistors offer high current handling and precise analog control.
- CMOS transistors provide low power consumption and high integration density for digital logic.
- DMOS transistors are optimized for high-voltage and high-current power applications.
For BCD devices to meet performance expectations, proper process control measures are needed, especially in the case of silicon-chromium (SiCr) thin films.
SiCr films play a critical role in BCD technology, primarily as precision resistive elements within analog and power management circuits (Figure 1.). SiCr resistors offer high stability, low temperature coefficient resistance (TCR), and excellent linearity, making them ideal for applications requiring accurate voltage and current control. Given the stringent reliability standards for BCD technology as demanded by the automotive industry and others, SiCr deposition must exhibit high reproducibility and minimal defectivity to support high-yield manufacturing and robust device performance under thermal and electrical stress.
Figure 1. Schematic of the BCD process, with SiCr film identified.
Uniformity across the wafer and repeatability between lots are critical. After all, minor thickness or compositional variations can lead to resistance drift which impacts analog accuracy and long-term reliability. Tight process control during the deposition step—including chamber stability, target conditioning, and plasma uniformity—ensures consistent film morphology and stoichiometry.
During SiCr sputtering, the precise regulation of specialty gas flow, in particular reactive gases such as nitrogen or oxygen, is critical, as their partial pressures influence plasma chemistry and the kinetics of silicide formation on the substrate. This silicide layer governs nucleation and grain growth, which directly affects grain boundary spacing and, consequently, TCR. Variations in gas flow can alter the stoichiometry and microstructure of the SiCr film, leading to shifts in TCR behavior, including the onset of a pronounced negative coefficient if the process is not tightly controlled.
Given the importance of these demands, manufacturers need the right tools on hand to maintain proper process control and optimize the performances of their BCD devices. In this article we will discuss the application of picosecond ultrasonic technology in two parts: one as a robust thickness metrology solution for qualifying SiCr deposition process and the second for excursion monitoring in BCD devices.
About Picosecond Ultrasonic Technology
Picosecond ultrasonic technology (PULSE™ technology) is a non-contact, non-destructive pump-probe laser acoustic technique for the measurement of metal film thickness. It is a proven workhorse in semiconductor fabs around the world. A 0.1ps laser pulse (pump) is focused to a small (~ 8´10mm2) spot onto a wafer surface to create a sharp acoustic wave. The acoustic wave travels away from the surface through the film at the speed of sound. At the interface with another material, a portion of the acoustic wave is reflected and comes back to the surface while the rest is transmitted. The probe pulse detects this reflected acoustic wave as it reaches the wafer surface. One can detect the change of optical reflectivity that is caused by the strain of the acoustic wave or alternatively detect, using a position sensitive detector (PSD), the deflection of the reflected probe beam that is caused by the deformation of the surface due to the acoustic wave. Both modes, reflectivity (REF) and PSD, are used in characterizing metal films. Knowing the speed of sound in the material, and the arrival time of the echoes, thickness is readily extracted using the first principles technique.
Film Thickness
With background on picosecond ultrasonic technology out of the way, we will turn our attention to the application of this technology as a robust thickness metrology solution for qualifying SiCr deposition process in BCD devices. To demonstrate this, we measured the nominal thickness of SiCr thin films using picosecond ultrasonic technology.
Figure 2a shows the raw data from the SiCr thin film. The acoustic echoes identified in the figure are used to calculate the thickness of the film using the speed of sound and round-trip transit time through the film. Nominally, textbook values for the longitudinal speed of sound would be used. In the case of SiCr films, the longitudinal speed of sound will vary from the bulk material and depend on the deposition process (sputtering, evaporation, etc.) and specific film composition (stoichiometry, density, etc.).
As a one-time calibration, we used cross-section transmission electron microscopy (TEM) to obtain SiCr film thickness and calculated the speed of sound for this specific process to be 69.7Å/ps. The modeled fit to the measurement is shown in Figure 2b.
Figure 2a. Raw data of reflectivity change vs time shown. The cross-wafer variation is identified by the shift in acoustic echoes.
Figure 2b. Modeled fit to measured data shown. The green curve represents the measurement, and the black curve represents the fit.
In Figure 3a, raw data from the DOE skew is shown. The shift in echo position between the different wafers demonstrates the sensitivity of the technique for monitoring the process. Within wafer uniformity profiles from 13 points across the wafer show consistent trends (Figure 3b).
Given the critical function of SiCr films in BCD device architecture, it is imperative to maintain highly uniform deposition with stringent process control to meet electrical and reliability specifications. Yield optimization is directly correlated with film uniformity as variations can significantly degrade device performance and long-term stability. As part of chamber qualification, more extensive sampling across the wafer, including to the edge, was performed (Figure 4). Those profiles are also consistent across the thickness skew.
Figure 3a. Raw data from the DOE thickness skew. Delta represents the skew in thickness from the target. The shift in echo position demonstrates the sensitivity for process monitoring
Figure 3b. Consistent cross wafer uniformity profiles for the three wafers.
Repeatability is a key metric in SiCr thin film metrology for ensuring robust process control and consistent device performance. Poor repeatability can obscure true process shifts, leading to incorrect corrective actions and potential yield loss. Gage capable repeatability measurements ensure compliance with automotive industry standards and are critical for long-term reliability. The dynamic repeatability data indicates performance is better than 0.5Å (1σ) and is more than sufficient to meet the process monitoring needs.
Figure 4. Forty-nine point wafer uniformity profiles for the three wafers, including measurements to the edge of the wafer. The profiles were consistent across the entire wafer.
As demonstrated, picosecond ultrasonic technology provides a precise, non-destructive method for measuring film thickness, validated against TEM calibration. The technique also offers exceptional repeatability and sensitivity, enabling manufacturers to monitor wafer-to-wafer and within-wafer uniformity with confidence. This capability is critical for maintaining tight process windows, as even minor deviations in thickness can lead to resistance drift and compromise analog precision. By integrating this metrology into chamber qualification and process monitoring, fabs can ensure consistent SiCr deposition, optimize yield, and meet stringent reliability standards.
Film quality
In picosecond ultrasonic technology, acoustic echoes are used to calculateSiCr film thickness. However, simultaneously available probe reflectivity data can be leveraged to provide information that can be used for process optimization (i.e., gas flow) and flagging process excursions. As such, this technique can be used to monitor the surface reflectivity of SiCr films; this application serves as a qualitative indicator of the film morphology and surface roughness and can be used for process control.
Figure 5. Surface reflectivity comparison for films having same target thickness but different reflectivity. Average reflectivity variation (top) across wafer is much higher than the thickness variation (bottom). Orange represents the lower flow rate, and blue represents the higher flow rate.
During the sputtering of SiCr films, gas flow has a strong influence on TCR as it impacts the film’s microstructure and stoichiometry (density and composition). This, in turn, determines the film’s stability, stress, and electromigration resistance in BCD applications. Uneven gas distribution causes local variations in thickness and composition leading to resistor mismatches and unpredictable TCR.
The surface reflectivity of the target wafer at two different gas flow rates is shown in Figure 5. Reflectivity data was collected at the same time as the acoustic data and shows the variation in surface reflectivity. At gas flow rate (b), the surface was more reflective corresponding to a smooth, dense film, whereas at flow rate (a), the reduced reflectivity indicates increased surface roughness which can degrade resistor uniformity and TCR stability.
Also, the thickness variation SiCr film is thinner at the higher N2 flow. N2 is known to affect silicide/nitride formation, grain spacing, etc., and impact both thickness and reflectivity. Studies are underway to characterize the impact of annealing temperature. The results are promising.
In summary, the surface quality of SiCr films plays an equally critical role in device stability and long-term performance. The study highlights how reflectivity measurements, captured alongside thickness data using the same picosecond ultrasonic platform, serve as a powerful indicator of film morphology and density. Variations in gas flow during sputtering were shown to significantly influence both reflectivity and thickness, underscoring the importance of precise control over deposition parameters. A smoother, more reflective surface correlates with improved resistor uniformity and predictable TCR behavior, while rougher films can degrade electrical performance.
Based on these results, we have demonstrated that reflectivity measurements, along with thickness measurements, can be leveraged for in-line monitoring to detect deviations in deposition parameters. By leveraging dual metrics—thickness and reflectivity—manufacturers gain a comprehensive, in-line process control solution that enables early detection of excursions and proactive corrections, ensuring robust SiCr thin film integration in advanced BCD architectures.
Conclusion
From automotive safety systems to medical imaging and consumer electronics, BCD technology enables the seamless integration of analog, digital, and power functions that modern applications demand. Yet, this versatility hinges on precise control of SiCr thin films whose stability and uniformity directly influence device reliability
Achieving this level of integration comes with significant manufacturing challenges, particularly in controlling SiCr film thickness and gas flow during sputtering, factors which directly impact resistor stability and temperature performance, which are critical for reliability in demanding environments. To overcome these hurdles, we propose using picosecond ultrasonic technology.
With picosecond ultrasonic technology, manufacturers have a powerful, non-destructive tool for monitoring thickness and reflectivity at the ready, one that ensures that SiCr films meets stringent performance standards. In doing so, manufacturers will be able to safeguard the integrity of BCD devices while supporting the continued evolution of new technologies across the automotive, medical, and consumer electronics sectors.
By Huayuan Li, Alex Hong, Johnny Mu, Timothy Kryman, and Priya Mukundhan
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In a world where high-bandwidth memory, GPUs, and advanced AI packages are all the rage, it is easy to forget the important role specialty devices play. These unsung heroes of modern life perform critical functions across a wide range of industries, including automotive, telecommunications, data centers, emerging AI hardware ecosystems, and consumer electronics, just like the smartphone in your hands, on your desk, or in your pocket. You know, the little pocket computer that never leaves your side.
And with new functions being added to consumer electronics with each new generation, the demand for specialty devices is on the rise. On the other end of the spectrum, manufacturers are facing an increasing number of challenges brought on by the growing complexity of these devices. Examples of this include SiC and GaN power devices, MEMS sensors, RF filters, photonics, and CMOS image sensors. We will cover all of these device types in this blog, the second in our three-part blog The Specialty Device Surge.
As discussed in part one of our series, the specialty segment is moving to larger wafer sizes. Not only does this transition promise higher throughput and improved economies of scale, it introduces new manufacturing and process control challenges, many of which are unique to each device category. Why? Each type of specialty device relies on unique materials, architectures, and process steps.
Across the industry, this complexity shows up in different ways. MEMS devices rely on a variety of materials or key processes depending on their core function: thick piezoelectric films, suspended mechanical structures, and near‑perfect plasma‑etched sidewalls, each requiring highly specialized deposition and metrology techniques. CIS manufacturing spans multiple bonded layers—pixel, CMOS, and microlens—each with its own set of defect, CD, and uniformity challenges that directly shape image quality. Power devices such as SiC and GaN introduce further hurdles: crystalline defects, trench‑shape control, epitaxial thickness uniformity, and surface‑quality demands that grow more difficult as these materials scale toward larger wafers. Photonics and co‑packaged optics push complexity even further, requiring precision across waveguides, doped films, microlenses, lasers, and the multi-die assembly process that integrates them into a single high-bandwidth module.
However, all these technologies share a simple truth: achieving high-volume production depends on advanced metrology, intelligent inspection, and tightly integrated feedback and feed‑forward control. Combined, these tools allow device makers to stay inside increasingly narrow process windows as specialty devices scale, diversify, and enter high‑volume production.
But first, let’s dive into the challenges facing specialty devices. We will begin by focusing on MEMS.
MEMS
The top five MEMS device types are pressure sensors, gyroscopes, accelerometers, microphones, and surface acoustic wave (SAW)/bulk acoustic wave (BAW) radio frequency (RF) MEMS. These are known as the Billion Dollar Club. And with good reason. Each of these devices is responsible for sales in excess of $1 billion per year. Impressive.
MEMS devices rely on either a unique material or unit process to deliver their core functionality. In the case of pressure sensors and microphones, the unique material is typically polysilicon or dielectric membranes or piezo films, which require very specific chemical or physical vapor deposition techniques to achieve the required film thickness and orientation to maximize the piezo coefficient for the material. For gyroscopes and accelerometers, the device relies on the formation of what are called interdigitated comb fingers; these capacitors rely on precise plasma etch techniques to deliver vertical side walls. However, any tilt can result in poor device operation.
Finally, there are the class of RF filter devices known as BAW devices. These devices rely on precisely deposited piezo films of either AlN or scandium doped aluminum nitride. In BAW devices, thickness and film orientation control the frequency of operation; as such, thickness uniformity across the entire wafer is essential keeping each device operating at the required frequency.
CMOS Image Sensors (CIS)
Today’s CIS devices are anywhere from 6µm to 10µm tall, with pixels in the image layer and separated from one another by approximately 100nm-wide isolation trenches.
Pixel formation relies on several dopant implant steps. The isolation trenches have sidewalls specifically engineered to increase total internal reflection, thereby increasing the light capturing efficiency of the pixel, and minimize so-called dark noise (the movement of electrons within the pixel when no light is present). The latter typically involves increasing the work function of the materials along the sidewalls of the isolation trenches.
In the formation of a pixel imager, multiple challenges, from epitaxial layer thickness and dopant uniformity metrology to isolation trench defect inspection and CD and shape metrology, exist. Each challenge must be addressed to create the perfect pixel for imaging.
Several unique metrology and inspection steps are needed for each layer. Layer 1 of the CIS is the pixel layer, layer 2 is the CMOS layer which is usually hybrid bonded to the pixel layer, and layer 3 features the microlens array which is either bonded or manufactured directly on the pixel wafer.
SiC and GaN Power Devices
In recent years SiC has seen a tremendous surge in popularity given its use for switching high voltages in EV motors. Today, SiC is in production at 200mm. However, some manufacturers have started to produce 300mm SiC wafers for applications that take advantage of the material’s unique thermal conductivity.
Inspection and metrology play key roles in the production of SiC power devices. First of all, inspection is used to identify latent or killer crystalline defects in the initial substrate and subsequent epitaxial SiC layers. Then, regular particle defect inspection and all-surface inspection is performed to catch additional defects on the edge or backside of the wafers. Multiple particle defect inspections are carried out throughout the remainder of the high-volume manufacturing process.
Now on to metrology. The ability to conduct accurate measurements plays a key role in understanding the thickness, dopant concentration, and uniformity of the epitaxial layers grown on the initial substrate. The importance of metrology does not end there. Across the remainder of the process flow, CD metrology and trench shape metrology play a part in ensuring device yield and performance.
Unlike SiC, GaN technologies migrated to 300mm wafers earlier. For GaN power devices, the challenge involves identifying crystalline defects, surface roughness metrology, AlGaN layer homogeneity, and CD metrology.
The key need for original equipment manufacturers supporting customers in this segment is the ability to deliver inspection and metrology technologies that can handle these materials and associated wafer thicknesses, while also performing necessary inspection or metrology steps at cost-of-ownership price points for power devices. After all, these technologies need to offer manufacturers economically viable alternatives to ever-improving silicon power devices.
Photonics and Co-Packaged Optics
Photonics technologies have been around for decades, but they have evolved with the times. Now you can find photonics in a growing number of applications, including laser printing and xerography, facial recognition, and several telecommunication-based applications. Today, however, we’re seeing a new demand driver for this technology: AI.
Current AI devices communicate via standard metal traces. However, the increasing bandwidth requirements of AI chipsets and the power dissipation incurred from the use of copper wiring within data centers have combined to create a demand for a high-speed technology that consumes little power: silicon photonics.
Figure 1: Left to right, examples of V-grooves, basic waveguide geometry, and refractive and diffractive micro-lens structures. Each physical device brings with it its own set of key inspection and metrology requirements.
Silicon photonics replace these metal traces with optical waveguides that use light, not electrons, to carry information. In the case of co-packaged optics (CPO) which are directly integrated with chips, photonics provides ultra-high-bandwidth, low-power, light-based data transmissions. CPO combines laser sources with waveguide-based silicon chips, micro-lenses, and opto-electronic converters in a package that fits neatly on the modern panel level AI package. This one small module represents the cumulative challenges of multiple manufacturing segments under the umbrella of photonics and optics. Addressing these challenges requires V-groove inspection and metrology, waveguide metrology, micro-lens inspection and metrology, and a number of other areas including dopant uniformity (Figure 1). In the end, the ultimate success of any given CPO module relies on the assembly of all the die that go into it.
Conclusion
Whether the subject is MEMS structures demanding near perfect sidewalls, CIS stacks spanning multiple bonded layers, power devices pushing wide-bandgap materials to their limits, or photonics and co‑packaged optics, the common challenge manufacturers face is control. Across every specialty device category, success hinges on advanced metrology and inspection solutions that can precisely measure what matters most—shape, thickness, uniformity, defects, and material properties—at high throughput and low cost.
In the final blog of this three-part series, we’ll shift our attention from the challenges facing specialty devices to their solutions. We hope you will join us to learn more about these unsung heroes of modern life.
Christopher Haire is a marketing content specialist at Onto Innovation and a former business journalist.
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Abstract
Picosecond Ultrasonics (PULSE™) Technology has emerged as a leading metrology solution for characterizing single-layer and multilayer metal films in advanced semiconductor manufacturing [1]. As a non-contact, non-destructive technique, PULSE Technology has become the tool-of-record across multiple device segments, including logic, radio frequency (RF), memory, microelectromechanical systems (MEMS), and flash memory. Its ability to measure both film thickness and elastic modulus [2,3] in-line makes it indispensable for process control and material characterization.
Backside metallization (BSM) is essential in semiconductor fabrication, particularly for power electronics, logic ICs, and advanced memory devices. It involves depositing metal layers on the wafer’s reverse side to improve electrical conductivity, thermal dissipation, and mechanical stability. As device architecture becomes more complex, precise control and measurement of BSM layers are critical for ensuring performance and reliability. Driven by demand from semiconductors, photovoltaic, MEMS, and LED sectors, the BSM market is expanding rapidly [4]. Technologies such as PVD, CVD, electroplating, and sputtering enable tailored metal stacks, but they also pose metrology challenges—especially for non-destructive, multilayer characterization. These metal layers typically range from 50 nm to 3 µm in thickness, with total stack thicknesses reaching up to 5 µm.
Accurate characterization of BSM layers is essential for ensuring device reliability, performance, and manufacturing yield. Traditional metrology techniques such as scanning electron microscopy (SEM), atomic force microscopy (AFM), four-point probe, X-ray reflectometry (XRR), and X-ray fluorescence (XRF) often face limitations in throughput, destructiveness, thickness limitations, or sensitivity to surface roughness. In contrast, Picosecond Ultrasonics offers a compelling alternative, providing high-precision measurements across a wide thickness range with micron-scale spatial resolution. Its ability to simultaneously resolve multiple layers in a single measurement, even on rough or non-planar surfaces, makes it particularly well-suited for BSM applications.
In this paper, we demonstrate the application of Picosecond Ultrasonics to backside metallization metrology. We present data showing its capability to measure both single-layer and multilayer metal stacks with excellent repeatability, long-term stability, and high throughput. The technology’s small spot size—on the order of microns—enables measurements on small pads as small as 15 µm, improving spatial resolution and enabling in-line monitoring on product wafers. Furthermore, advanced features such as dual modulation, crossed polarization, and adaptive measurement controls enhance performance on challenging surfaces, including aluminum and complex BSM stacks.
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Abstract
Surface Relief Grating (SRG) waveguides have been adopted as the mainstream solution in the industry, for its slim profile, high transparency, and large field of view. Furthermore, with their superior optical performance and mass production potential, SRG waveguides have emerged as a critical pathway for high‑performance augmented reality (AR) and mixed reality (MR) displays. In the mass production of SRG optical waveguides, where multi‑layer and double‑sided fabrication demand strict process control of overlay, geometry, and defects. We present a full process control solution for SRG mass production, combining optical critical dimension (OCD) metrology for the critical parameters of SRGs such as the grating depth, slanted angle, and periods, picosecond ultrasonic (PULSE™) technology for the metal film thickness measurement, image‑based overlay (IBO) on the IVS™ platform for precise overlay control, automated optical inspection based Dragonfly® system for the defects integrated throughout the entire SRG manufacturing process. OCD shows sub‑nanometer deviation and excellent matching with AFM, with high dynamic stability. PULSE™ technology ensures rapid, non‑contact measurement and uniformity control of chromium (Cr) and aluminum (Al) hard masks. Overlay precision reaches 0.26 nm (X) and 0.18 nm (Y) at 3σ, well within sub‑100 nm alignment requirements. Automated inspection captures >95% of submicron defects with low false positives. This framework has been validated in mass production at leading AR/MR manufacturers, enabling fully digitalized closed‑loop process control and supporting large‑scale, high‑yield SRG waveguide manufacturing.
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