Dragonfly® G3 System
The Dragonfly G3 system is resetting the industry’s expectations for throughput, accuracy and reliability. Combining 2D and 3D technologies, the system detects yield-robbing defects and measures features critical for today’s front-end and packaging technologies.

Product Overview
The Dragonfly G3 system utilizes line scan-based 2D imaging technology to provide fast, reliable inspection for sub-micron defects, meeting both current R&D and future production needs. It features multi-illumination channels, including brightfield/darkfield, high-speed IR for embedded defects and Clearfind® Technology for non-visual residue detection. For specialty markets like CMOS image sensors (CIS), it uses oblique angle illumination, sophisticated image processing and machine-learning algorithms to detect low contrast defects in the active pixel sensor area.
Optional 3D metrology sensors include the latest 3Di™ technology, delivering fast, precise bump height metrology. Discover Software visualizes the massive amounts of bump data, correlating process variations to improve yields. TrueADC software enables real time automatic classification of critical defects and reduces nuisance defects. The Dragonfly G3 system, with optional edge and backside inspection via the EB40 module, offers a comprehensive all-surface inspection solution for next generation technology challenges.
Applications
- Redistribution layers (RDL): after develop, after etch
- Reconstituted and bonded wafers
- Micro bumps and Cu pillars
- Post saw
- Gel and waffle pack inspection
- Post probe and testing
- OQA
Hybrid Bonding Process Control Solution
Hybrid bonding enables ultra-dense 3D memory interconnects with up to 1,000x more connections than microbumps. Achieving high yield requires stringent process control, including monitoring topography and detecting particles, cracks and voids. Measuring dishing in copper pads provides valuable insight into surface conditions. Together, these process control insights contribute to improved device reliability and performance.

Enabling In-Line Process Control for Hybrid Bonding Applications
As demand grows for high-performance computing (HPC) and AI-driven applications, manufacturers are turning to hybrid bonding to enable the ultra-dense 3D integration required for next-generation chip architectures. This advanced packaging technology presents significant process challenges. Surface preparation must be precisely controlled to eliminate particles, excess recess, and copper pad dishing, all of which can compromise bond quality. During pre-annealing, particle-induced gaps and wide bonding gaps can prevent proper wafer contact. Post-annealing, the formation of dielectric and metal voids introduces further risks to electrical performance and long-term reliability.

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