F30™ System
The F30 system is designed to blur the lines between dark field micro inspection and traditional macro inspection, providing automated defect inspection for front-end and outgoing quality (OQA) applications.
Product Overview
The F30 automated defect inspection system combines high resolution and throughput to drive fab yield and productivity. A five-objective turret enables resolution-throughput flexibility, while its multi-channel illumination including brightfield, darkfield, high-angle ring light, and IR-Review addresses the requirements for today’s multi-process inspection applications. Equipped with an advanced productivity suite (waferless recipe creation, simultaneous FOUP, recipe server and tool matching), the F30 System redefines inspection cost of ownership expectations. The system can handle 100mm – 300mm wafers can be paired with the edge and backside module (EB40) to provide an all-surface inspection solution.
Applications
- After develop inspection (ADI)
- Post CMP inspection
- After etch inspection
- Fab Outgoing QA
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Celero™ PL System
The Celero PL system is designed for subsurface defect inspection and classification for silicon carbide (SiC) and gallium nitride (GaN) based wafers and compound semiconductor materials.
Product Overview
The Celero PL system utilizes a laser-based phase detection and imaging capability that leverages custom optics and image processing algorithms to enable best in class throughput and sensitivity for silicon carbide and gallium nitride-based materials on 100mm to 300mm wafer sizes. Leveraging multiple light sources and sensor channels, the system can detect, measure and image a broad variety of subsurface crystalline defects, associated with bulk wafers and epitaxial layers, surface particles, scratches, pits, surface contamination, stains, point or bulk wafer stress, voids/inclusions, including chips and cracks at the edge of the wafer.
Applications
- Frontside / backside / edge / subsurface defectivity and contamination
- Crystalline defectivity in III-V substrates and epitaxial layers
- Thick wafer / seed wafer surface and sub-surface defectivity
- Substrate-to-epitaxial layer defect mapping (sub-defect mapping)
- Wafer based microLED / VCSEL / EE laser materials
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PrimaScan™ P System
The PrimaScan P System provides all-surface defect and contamination inspection with imaging capability for glass panel substrates.
Product Overview
As panel-level-packaging (PLP) transition from copper-clad laminates (CCL) to glass, the industry must adapt to ensure starting substrates are free of killer defects and contamination or latent defects that may result in yield loss or scrapped panels at later stages in the process flow. The PrimaScan P system is specifically designed to address incoming glass panel quality control for both the advanced IC substrate (AICS) and fan-out panel level processing (FOPLP) segments.
The PrimaScan P system delivers unique laser-based scanning and imaging via proprietary optics and sensing technologies for the reliable inspection of nanometer sized defects for either R&D or high-volume manufacturing environments. Utilizing multiple channel inspection technologies, the system can detect, measure and image surface particles, scratches, pits, surface contamination, stains, film or bulk panel stress, voids/inclusions, including chips and cracks at the edge of the panel.
Applications
- Incoming unpatterned glass panel quality inspection
- Blanket photoresist, dielectric or metallic coated panels
- Buried defects and voids in transparent and semi-transparent blanket films
- Across panel stress and induced point stress
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PrimaScan™ R&D System
The PrimaScan R&D System is a stand-alone, manual load version of the PrimaScan automated wafer defect and contamination inspection system that has been specifically designed with R&D and lab environments in mind.
Product Overview
The PrimaScan R&D system offers a smaller spot size and higher pixel resolution than its high volume production counterpart tools. The flexibility in sample handling options combined with the multiple sensing channels and higher resolution imaging makes this the ideal tool for R&D and lab environments. Similar to the other tools in the PrimaScan line, the PrimaScan R&D system offers reliable inspection of nanometer sized defects on a variety of opaque and transparent/semi-transparent substrates and samples suitable for either R&D or lab environments. The system can detect, measure, characterize and image surface particles, scratches, pits, bumps, surface contamination, film or bulk wafer stress, voids/inclusions, including chips and cracks at the wafer edge.
Designed with versatility in mind the PrimaScan R&D system can handle a variety of wafer sizes and substrate types including film frame, photomask and sample tray.
Applications
- Opaque or transparent wafer incoming quality (ICQ) inspection
- Process monitor wafer particle and contamination inspection
- Unpatterned blanket photoresist, dielectric or metallic coated wafer defect inspection
- Subsurface defectivity inspection for transparent and semi-transparent films and substrates
- Glass wafer defect and contamination inspection for microfluidics, microlens arrays for AR/VR/MR, flat optics, etc.
- Post-CMP or post-grind defect inspection
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EB40™ Module
The EB40 Module combines edge and backside inspection into one tool with the option to be paired with an inspection system to provide a high throughput all surface inspection solution.
Product Overview
The Class 1 certified EB40 module offers combined edge and backside inspection and is also available as separate edge (E40) and backside (B40) modules. These modules provide brightfield and darkfield inspection to detect defects on the entire bevel and backside, covering Zone 1 to Zone 5. This enables faster root-cause analysis of defects that can migrate to the wafer interior, impacting die yield.
The EB40 module captures defect images on the fly, creates whole-wafer composite images, and integrates with SEM bevel review. All inspection and metrology results, including defect, whole wafer and SEM images can be analyzed together in a single database using Discover Defect software. Correlating EBR metrology with defectivity data, SEM data and micro-inspection results is just the beginning of what Discover software can do. In addition to advanced on-tool defect binning, real-time edge ADC classification can be assigned to defects prior to manual offline review using Discover Review software.
Applications
- EDGE INSPECTION
- Lithography process monitoring
- Cracks/Chips, Slurry, cleaning contaminants and residual films
- EBR Metrology
- Bonded wafer adhesive inspection
- BACKSIDE INSEPCTION
- Scratches
- Chuck and end effector signatures
- Backside particles and residues
- Wafer level pattern detection
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Firefly® G3 System
The Firefly G3 system provides automated inspection and 3D metrology for advanced IC substrates and panel level packaging, delivering high resolution and productivity for demanding applications like high-performance computing (HPC), artificial intelligence (AI), cloud computing and machine/deep learning.
Product Overview
The Firefly G3 platform offers multiple imaging modes, including Onto Innovation’s patented Clearfind® Technology, a technique to detect residue defects on metal and metal defects on organic layers. The combination of high sensitivity inspection, 2D/3D metrology and on tool color image capture capability in a single platform reduces capital investment requirements and provides a reliable pathway for panel-based process applications that require high I/O counts and multiple-chip integration.
Integration with Onto Innovation’s Discover® Defect and TrueADC® software quickly turns defect data into actionable process control, improves defect classification and reduces manual review. It enables our customers to develop, learn and analyze new processes reliably while significantly improving their product delivery time to market.
Applications
- Advanced IC Substrates (AICS): CCL and Glass
- Fan-out Panel Level Packaging (FOPLP)
- Interposers
- Embedded Die substrates/ Interposer
- 2.5D/3D integration
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Adaptive Shot Lithography Solution
Die shift on reconstituted panels can significantly impact both productivity and yield. To address this challenge, we use a parallel die placement measurement process and advanced analytics to provide a means to balance productivity against yield. Our integrated lithography cell, featuring Firefly inspection, StepFAST software, and JetStep Lithography, delivers industry-leading throughput and yield for fan-out panel level packaging.
Overcoming FOPLP Die Placement Error
It is well understood that advanced packaging applications require high performance, low cost, increased functionality and improved reliability that 2.5D and 3D packaging solutions provide. Fan-out panel-level packaging (FOPLP) is one of the technologies that has the potential to meet these packaging requirements.
Adaptive Overlay Control
During the processing of organic (CCL) advanced IC substrates (AICS) the substrates become distorted which impacts the overlay of Via to RDL pad structures. To solve this problem, the stepper must adjust the alignment solution to match the previous layer’s distortion by measuring the overlay. Proprietary software provides the user with the ability to adjust each zone of the AICS with independent offsets.
Analysis of Pattern Distortion by Panel Deformation
The growing demand for heterogeneous integration is driven by the 5G market. This includes smartphones, data centers, servers, high-performance computing (HPC), artificial intelligence (AI) and internet of things (IoT) applications. Next generation packaging technologies require tighter overlay to accommodate larger package sizes with fine-pitch chip interconnects on large-format flexible panels.
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