In a world where high-bandwidth memory, GPUs, and advanced AI packages are all the rage, it is easy to forget the important role specialty devices play. These unsung heroes of modern life perform critical functions across a wide range of industries, including automotive, telecommunications, data centers, emerging AI hardware ecosystems, and consumer electronics, just like the smartphone in your hands, on your desk, or in your pocket. You know, the little pocket computer that never leaves your side.
And with new functions being added to consumer electronics with each new generation, the demand for specialty devices is on the rise. On the other end of the spectrum, manufacturers are facing an increasing number of challenges brought on by the growing complexity of these devices. Examples of this include SiC and GaN power devices, MEMS sensors, RF filters, photonics, and CMOS image sensors. We will cover all of these device types in this blog, the second in our three-part blog The Specialty Device Surge.
As discussed in part one of our series, the specialty segment is moving to larger wafer sizes. Not only does this transition promise higher throughput and improved economies of scale, it introduces new manufacturing and process control challenges, many of which are unique to each device category. Why? Each type of specialty device relies on unique materials, architectures, and process steps.
Across the industry, this complexity shows up in different ways. MEMS devices rely on a variety of materials or key processes depending on their core function: thick piezoelectric films, suspended mechanical structures, and near‑perfect plasma‑etched sidewalls, each requiring highly specialized deposition and metrology techniques. CIS manufacturing spans multiple bonded layers—pixel, CMOS, and microlens—each with its own set of defect, CD, and uniformity challenges that directly shape image quality. Power devices such as SiC and GaN introduce further hurdles: crystalline defects, trench‑shape control, epitaxial thickness uniformity, and surface‑quality demands that grow more difficult as these materials scale toward larger wafers. Photonics and co‑packaged optics push complexity even further, requiring precision across waveguides, doped films, microlenses, lasers, and the multi-die assembly process that integrates them into a single high-bandwidth module.
However, all these technologies share a simple truth: achieving high-volume production depends on advanced metrology, intelligent inspection, and tightly integrated feedback and feed‑forward control. Combined, these tools allow device makers to stay inside increasingly narrow process windows as specialty devices scale, diversify, and enter high‑volume production.
But first, let’s dive into the challenges facing specialty devices. We will begin by focusing on MEMS.
MEMS
The top five MEMS device types are pressure sensors, gyroscopes, accelerometers, microphones, and surface acoustic wave (SAW)/bulk acoustic wave (BAW) radio frequency (RF) MEMS. These are known as the Billion Dollar Club. And with good reason. Each of these devices is responsible for sales in excess of $1 billion per year. Impressive.
MEMS devices rely on either a unique material or unit process to deliver their core functionality. In the case of pressure sensors and microphones, the unique material is typically polysilicon or dielectric membranes or piezo films, which require very specific chemical or physical vapor deposition techniques to achieve the required film thickness and orientation to maximize the piezo coefficient for the material. For gyroscopes and accelerometers, the device relies on the formation of what are called interdigitated comb fingers; these capacitors rely on precise plasma etch techniques to deliver vertical side walls. However, any tilt can result in poor device operation.
Finally, there are the class of RF filter devices known as BAW devices. These devices rely on precisely deposited piezo films of either AlN or scandium doped aluminum nitride. In BAW devices, thickness and film orientation control the frequency of operation; as such, thickness uniformity across the entire wafer is essential keeping each device operating at the required frequency.
CMOS Image Sensors (CIS)
Today’s CIS devices are anywhere from 6µm to 10µm tall, with pixels in the image layer and separated from one another by approximately 100nm-wide isolation trenches.
Pixel formation relies on several dopant implant steps. The isolation trenches have sidewalls specifically engineered to increase total internal reflection, thereby increasing the light capturing efficiency of the pixel, and minimize so-called dark noise (the movement of electrons within the pixel when no light is present). The latter typically involves increasing the work function of the materials along the sidewalls of the isolation trenches.
In the formation of a pixel imager, multiple challenges, from epitaxial layer thickness and dopant uniformity metrology to isolation trench defect inspection and CD and shape metrology, exist. Each challenge must be addressed to create the perfect pixel for imaging.
Several unique metrology and inspection steps are needed for each layer. Layer 1 of the CIS is the pixel layer, layer 2 is the CMOS layer which is usually hybrid bonded to the pixel layer, and layer 3 features the microlens array which is either bonded or manufactured directly on the pixel wafer.
SiC and GaN Power Devices
In recent years SiC has seen a tremendous surge in popularity given its use for switching high voltages in EV motors. Today, SiC is in production at 200mm. However, some manufacturers have started to produce 300mm SiC wafers for applications that take advantage of the material’s unique thermal conductivity.
Inspection and metrology play key roles in the production of SiC power devices. First of all, inspection is used to identify latent or killer crystalline defects in the initial substrate and subsequent epitaxial SiC layers. Then, regular particle defect inspection and all-surface inspection is performed to catch additional defects on the edge or backside of the wafers. Multiple particle defect inspections are carried out throughout the remainder of the high-volume manufacturing process.
Now on to metrology. The ability to conduct accurate measurements plays a key role in understanding the thickness, dopant concentration, and uniformity of the epitaxial layers grown on the initial substrate. The importance of metrology does not end there. Across the remainder of the process flow, CD metrology and trench shape metrology play a part in ensuring device yield and performance.
Unlike SiC, GaN technologies migrated to 300mm wafers earlier. For GaN power devices, the challenge involves identifying crystalline defects, surface roughness metrology, AlGaN layer homogeneity, and CD metrology.
The key need for original equipment manufacturers supporting customers in this segment is the ability to deliver inspection and metrology technologies that can handle these materials and associated wafer thicknesses, while also performing necessary inspection or metrology steps at cost-of-ownership price points for power devices. After all, these technologies need to offer manufacturers economically viable alternatives to ever-improving silicon power devices.
Photonics and Co-Packaged Optics
Photonics technologies have been around for decades, but they have evolved with the times. Now you can find photonics in a growing number of applications, including laser printing and xerography, facial recognition, and several telecommunication-based applications. Today, however, we’re seeing a new demand driver for this technology: AI.
Current AI devices communicate via standard metal traces. However, the increasing bandwidth requirements of AI chipsets and the power dissipation incurred from the use of copper wiring within data centers have combined to create a demand for a high-speed technology that consumes little power: silicon photonics.

Figure 1: Left to right, examples of V-grooves, basic waveguide geometry, and refractive and diffractive micro-lens structures. Each physical device brings with it its own set of key inspection and metrology requirements.
Silicon photonics replace these metal traces with optical waveguides that use light, not electrons, to carry information. In the case of co-packaged optics (CPO) which are directly integrated with chips, photonics provides ultra-high-bandwidth, low-power, light-based data transmissions. CPO combines laser sources with waveguide-based silicon chips, micro-lenses, and opto-electronic converters in a package that fits neatly on the modern panel level AI package. This one small module represents the cumulative challenges of multiple manufacturing segments under the umbrella of photonics and optics. Addressing these challenges requires V-groove inspection and metrology, waveguide metrology, micro-lens inspection and metrology, and a number of other areas including dopant uniformity (Figure 1). In the end, the ultimate success of any given CPO module relies on the assembly of all the die that go into it.
Conclusion
Whether the subject is MEMS structures demanding near perfect sidewalls, CIS stacks spanning multiple bonded layers, power devices pushing wide-bandgap materials to their limits, or photonics and co‑packaged optics, the common challenge manufacturers face is control. Across every specialty device category, success hinges on advanced metrology and inspection solutions that can precisely measure what matters most—shape, thickness, uniformity, defects, and material properties—at high throughput and low cost.
In the final blog of this three-part series, we’ll shift our attention from the challenges facing specialty devices to their solutions. We hope you will join us to learn more about these unsung heroes of modern life.
Christopher Haire is a marketing content specialist at Onto Innovation and a former business journalist.
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Dragonfly® G5 System
The Dragonfly G5 system is engineered for inline process control of leading-edge advanced packaging technologies. As the latest generation pattern inspection system in the Dragonfly series, it delivers unparalleled accuracy in detecting submicron defects and performing high-resolution 3D measurements.
Product Overview
Designed to meet the demands of advanced semiconductor technologies, the Dragonfly G5 system is purpose-built to deliver high-performance, reliable inspection and metrology across complex heterogeneous integration processes. Leveraging next generation high speed line scan 2D imaging and custom-engineered objectives, the system achieves over 3X throughput improvement compared to its predecessor, with submicron sensitivity down to 150nm.
Continuing the legacy of innovation, the Dragonfly G5 system introduces a multi-angle illumination channel that significantly improves signal-to-noise ratio for faint defect detection. Combined with powerful AI-driven algorithms, it enhances both the detectability and classification of critical, yield-impacting defects–empowering fabs to maintain quality and accelerate time-to-yield.
The Dragonfly G5 system expands process control flexibility for wafer-to-wafer and die-to-wafer bonding by integrating high-speed IR imaging to detect sub-surface defects. It incorporates the latest generation of 3Di™ technology, extending bump height metrology capabilities to support next-generation microbumps essential for 3D integration. This enables additional inspection and metrology touchpoints across increasingly complex packaging architectures.
Applications
- Hybrid Bonding
- Redistribution Layers (RDL): after develop, after etch
- BS/FS Pad CMP
- TSV Reveal
- Micro bumps and Cu pillars
Hybrid Bonding Process Control Solution
Hybrid bonding enables ultra-dense 3D memory interconnects with up to 1,000x more connections than microbumps. Achieving high yield requires stringent process control, including monitoring topography and detecting particles, cracks and voids. Measuring dishing in copper pads provides valuable insight into surface conditions. Together, these process control insights contribute to improved device reliability and performance.
Enabling In-Line Process Control for Hybrid Bonding Applications
As demand grows for high-performance computing (HPC) and AI-driven applications, manufacturers are turning to hybrid bonding to enable the ultra-dense 3D integration required for next-generation chip architectures. This advanced packaging technology presents significant process challenges. Surface preparation must be precisely controlled to eliminate particles, excess recess, and copper pad dishing, all of which can compromise bond quality. During pre-annealing, particle-induced gaps and wide bonding gaps can prevent proper wafer contact. Post-annealing, the formation of dielectric and metal voids introduces further risks to electrical performance and long-term reliability.
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If you’ve been following the evolution of advanced packaging, you know that the industry is pushing boundaries like never before. From high-performance computing to industry-upending AI devices, the demand for smaller, faster, and more powerful chips is driving innovation at every level. One of the unsung heroes in this transformation: Glass carriers.
These carriers are becoming essential for applications involving high-bandwidth memory (HBM), 2.5D/3D integration, and chiplet architectures. During the manufacturing process, glass carriers serve as mechanical support for thin wafers and panel-level packages. Why? Glass carriers are noted for their warpage resistance, superior rigidity, and thermal stability. This combination of glass’ exceptional flatness and rigidity enables the precise placement of dies and interposers. Additionally, glass is optically transparent, which allows through-glass alignment during bonding and stacking, a critical capability for 3D integration where multiple layers must be accurately registered.
The benefits of glass carriers, however, come with several challenges, none of which should come as a surprise to anyone who has ever handled glass, whether in the fab or at home. Glass is fragile and, as such, is prone to surface defects, subsurface inclusions, and residual stress. Each of these can negatively impact die attachment quality, interconnect reliability, and die yield.
Let’s take a look at three major yield-killing culprits.
Surface defects such as particles, pits, and scratches are among the most common issues and may occur during glass carrier handling and processing, compromising the structural integrity and performance of advanced packaging assemblies (Figure 1). Particles can interfere with the bonding process, leading to poor adhesion or electrical discontinuities, while pits and scratches can propagate stress points that weaken the carrier during thermal cycling or molding.
However, subsurface inclusions and organic contamination, which are often introduced during reclaim or cleaning, pose more critical challenges. Inclusions within the glass can create localized stress concentrations, while organic residues can reduce UV transmission and cause bonding failures. These contaminants are particularly problematic in high-density interconnect environments where optical clarity and surface purity are critical.

Figure 1: Common glass carrier defects
In addition to surface and subsurface defects, residual stress represents a concern. Over time, these stress points, manifesting during thermal processing or mechanical handling, can lead to cracks or delamination, undermining the thermo-mechanical integrity of the entire package.
These potential challenges are compounded each time a glass carrier is reused in an effort to reduce overall packaging costs. Fortunately, technologies have been developed to address this obstacle. These technologies integrate AI-driven defect classification, real-time analytics, and adaptive scanning modes to maintain throughput without sacrificing accuracy, enabling manufacturers to detect surface anomalies, subsurface inclusions, and stress-induced defects with unprecedented precision.
Enabling Defect-Free Glass Carriers
Today’s wafer-based inspection platforms utilize laser scatterometry and imaging techniques to inspect for nanometer sized defects on a variety of opaque and transparent/semi-transparent substrates. These substrates may be suitable for either R&D or high-volume advanced IC substrate (AICS) and fan-out panel level processing (FOPLP) environments. Proprietary inspection technology with multiple detection channels and advanced signal processing algorithms is applied to achieve accuracy and reliability in glass carrier inspection.

Figure 2: Results of top (blue) and bottom (red) defect mapping.
With each channel optimized to capture unique scattering and reflection signatures, the technology differentiates between surface and subsurface defects, as well as stress-related anomalies, with remarkable accuracy. Surface particles, scratches, pits, bumps, surface contamination, film or bulk wafer stress, voids/inclusions can be detected, measured, characterized, and imaged. One of the most significant capabilities of this technology is the ability to conduct simultaneous top, bottom, and internal defect mapping, a critical need for transparent and semi-transparent substrates where defects can occur across multiple planes (Figure 2).
Beyond defect detection, Angstrom-level film thickness measurement provides precise control over surface coatings and residual layers. This capability is particularly valuable in the glass reclaim process where even minor variations in film thickness can impact UV transmission and bonding performance. By enabling accurate defect detection and grading, only glass carriers meeting stringent quality standards are returned to production.
By introducing technologies that mitigate risks by providing comprehensive defect mapping and stress analysis, manufacturers are able to maintain the mechanical and thermal integrity required for next-generation devices. This capability is especially valuable in markets such as AI devices, high-performance computing, and automotive electronics where reliability is non-negotiable. With this combination of advanced optical technology and robust algorithmic analysis, manufacturers can successfully achieve higher yields, lower costs, and greater confidence in their packaging processes.
Conclusion
As packaging complexity grows and the use of glass carriers increases, inspection systems that combine multi-depth defect mapping and stress analysis will become indispensable for ensuring yield and reliability in AI and HPC devices. With the explosive growth in AI-driven data centers and advanced packaging architectures, manufacturers need solutions that combine accuracy, speed, and cost efficiency. The laser-based wafer inspection technology discussed in this blog meets several glass carrier challenges head-on while enabling advanced packaging houses to maintain defect-free glass carriers in support of next-generation advanced packaging.
The future of glass carriers is clear: with the right technologies at the ready, manufacturers have the tools and the means to meet the growing needs of the AI and HPC markets.
Biography
Jason Lin is Director of Product Marketing at Onto Innovation.
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FAaST® CV/IV System
The FAaST system is a versatile, non-contact electrical metrology platform, with an option to combine micro and macro corona-Kelvin technologies together with digital surface photovoltage (SPV). It enables high-resolution dielectric and interface measurements across a wide range of dielectric materials, supporting both R&D and high volume manufacturing.
Product Overview
The primary application of non-contact CV metrology is monitoring dielectric properties during IC manufacturing. Unlike conventional electrical measurements, it requires no sample preparation, eliminating the need for MOS capacitor structures. This reduces metrology cost and enables fast data feedback in both R&D and manufacturing environments.
The corona-Kelvin method uses a corona discharge in air to deposit an electric charge (DQC) on the wafer surface. A vibrating Kelvin-probe then measures the resulting surface voltage (V), enabling determination of the differential capacitance (C= DQC/DV). By monitoring surface voltage in both dark and illuminated conditions, the system separates two key components: dielectric voltage (VD) and semiconductor surface potential (VSB), enabling determination of flat band voltage (VFB).
Analysis of the resulting charge-voltage data yields electrical parameters, including trap density (Dit), flat band voltage (Vfb), dielectric charge (Qtot), dielectric capacitance (CD), Equivalent Oxide Thickness (EOT), leakage current, and tunneling characteristics.
Applications
- Plasma damage monitoring
- Residual charge and non-visual defect inspection
- Diffusion furnace oxide and interface characterization
- High-K and low-K dielectric capacitance
- Mobile ion mapping
- Charge trapping and hysteresis
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Aspect® S System
The Aspect S system is a revolutionary in-line, non-destructive model-based infrared reflectometry system that enables critical process control of high aspect ratio structures, films and epitaxial structures. It meets the needs of leading-edge customers with its high speed and process coverage.
Product Overview
As more high aspect ratio processes are used in multiple industry segments, there are metrology needs for monitoring of related processes, including dimensions and properties of carbon film hard masks and etched 3D structures.
The Aspect S delivers high-throughput, low COO, non-contact, non-destructive measurements of dimensions and uniformity of layers and etched structures used in integrated circuit manufacturing. The small spot size makes the tool suitable for measurements of scribe line test structures as in-line process control. The unique technology and analysis capability simplifies system calibration requirements and removes the effect of substrate variations for key layer measurements.
While the software contains advanced features for measurement recipe and analysis model creation, it has a user-friendly interface and implementation that allows the fab customers to create and manage the recipe system for Aspect S tool fleets.

Thickness map from amorphous carbon film
Applications
- Carbon hardmask used on V-NAND devices and test wafers
- Deep trench etch for CIS and analog device chips
- Doping monitoring of SiGeB and SiP materials
- Film composition characterization
- On-device and blanket wafer materials characterization for EPI process
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OCD Solutions
A suite of OCD modeling software and computing hardware that enables the full capability and connectivity across all Onto OCD and thin film metrology systems, including Atlas, Aspect, Iris and IMPULSE systems.
Product Overview
Onto Innovation’s OCD technology offers powerful modeling and computing packages to support various phases of film and OCD measurement setup, data management, and fleet management. These capabilities include model building, runtime data analysis, system calibration, data analytics, data connectivity and management, spectrum management and fleet matching.
Onto OCD solutions consist of several modeling and computing components, including Ai Diffract™ modeling software, runtime onboard computer, offline modeler, offline model building clusters, and recipe & data management server. Each component seamlessly extends OCD capabilities to Onto’s standalone and integrated metrology systems, providing end-to-end capabilities from offline recipe support and development to fab-wide networking and connectivity for easy fleet management.
Learn more about each component below.
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Ai Diffract™ Software
AI-guided OCD modeling and analysis software for high accuracy in-line optical metrology and offline recipe development
Ai Diffract software is a powerful modeling, visualization and analysis software with an intuitive 3D modeling interface to simplify the building and visualization of today’s most complex semiconductor devices. It offers OCD modeling and advanced machine learning capabilities, next-generation real-time regression, offline sensitivity analysis tools and comprehensive GUI and structure input for true multi-variant modeling. Ai Diffract software’s proprietary fitting algorithms enable fast and accurate calculations for signal processing, helping ensure high fidelity model-based measurements. Automation features for spectral fitting, recipe optimization, and sensitivity analysis offer great user productivity. The first-in-market AI-guided engine synergizes physics-based modeling and machine learning to deliver the most robust solution with quick time to solution.
Ai Diffract Modeler is the offline analytical engine that allows users to create and edit recipes offline. It supports multiple users and can connect to Ai Diffract cluster for high intensity computing.
Ai Diffract Onboard is the on-tool runtime engine that maximizes tool throughput for complex use cases. It ensures rapid analysis without interfering with system operation or impacting throughput.
Ai Diffract Cluster is an enterprise scale computing server deployed for offline recipe development or in-line real-time regression. Optimized to support the workload of Ai Diffract software analysis, it scales based on fleet size, recipe numbers, and computing intensity.
Recipe Distribution Server (RDS) / Nexus Servers is a fab-wide networking and server system for fleet management and connectivity. RDS/Nexus servers provide connectivity and support to Ai Diffract recipe management and distribution, data/spectrum feed-forward and feedback, spectrum management, and fleet management.
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