A recent study shows the radio frequency (RF) filter market growing steadily by nearly $16 billion from 2019 to 2024 at a compound annual growth rate (CAGR) of approximately 20%, according to Technavio. The strong growth in the RF filter market is driven by the increased adoption of 5G technology, the surge in smartphones using 5G, and commercial and consumer devices dependent on internet of things (IoT) applications. Together, these factors are some of the most significant players driving society’s digital transformation.
However, the RF filter market is faced with many of the same challenges the semiconductor industry as a whole is experiencing, including the need to pack more into increasingly smaller spaces. In each successive generation of RF filters, the number of filters has not only steadily increased, the rising number of filters has led to a need for more stringent process monitoring and control. A frequency accuracy, 3σ of 0.1%, requires film thickness control within the same accuracy or better.
Let’s look at one RF filter component, a bulk acoustic wave (BAW) resonator. A BAW is a piezoelectric structure sandwiched between the top and bottom electrodes. The resonant frequency depends on the acoustic velocity and the thickness of the piezoelectric film, and the thickness of the electrode. The thickness of the top electrode as a mass loading layer can be dialed in to generate a frequency shift, which is often used to form a filter passband.
Since the RF filter process is directly correlated to thickness, extremely uniform films (~0.1% or better) need to be deposited. With the additional requirements of 5G to support higher frequencies and increased bandwidth, RF filter device manufacturers employ several different process knobs to tune the devices. For example, we see an increasing trend toward thinner layers to support higher frequencies, the adoption of Sc-doped piezoelectric materials to improve piezoelectric coupling and the addition of temperature compensation SiO2 layers to the stack to improve the temperature coefficient of the resonator.
The ability to trace the genealogy of all the components in an electronic device has been getting more complex for decades. For many industries — automotive, defense, medical and others — the need to locate the source of a problem in near real-time is paramount to gauging the extent of that problem. The extreme case is when the issue occurs with a product that already has been distributed and used in the field. Complicating matters is the fact that the current chip shortage is pushing chip designers to second- and third-tier suppliers for their inventory.
Tracking information is not easily done given the number of times material can change hands during the manufacturing life cycle. Designs can incorporate IP modules from Parties No. 1, No. 2, and No. 3 (figure 1). These designs are blended into a singular chip by the device’s Design House. This chip is then built at Front-end Foundries No. 1 or No. 2. The completed chip can be tested and partially assembled at OSAT A, B, or C. Finished assembly into a multi-chip module (MCM) or printed circuit board (PCB) can take place at Assembly House No. 1 or No. 2 (or happen at Customer A if they provide the IP for a design for a device that can be assembled by Finished Goods Maker No. 1) before it is finally sold by the Design House to the End User or Final Goods Manufacturer A, B, C, D and more for insertion in their end product, after which it is again tested before being sold to the end customer.
This is a very simplified example of how complex a supply chain can be, but it is illustrative nonetheless.
Virtual v. physical traceability
At some point in the supply chain, units receive a physical marker that enables traceability as it progresses through the remaining chain of manufacturing agents. Prior to the application of a marker, reliance on a part’s origin is a function of accounting and accurate recordkeeping. Although this seems simple enough, it is complicated by the transition of “ownership” of the chip as it moves through the supply chain.
Tracing a chip’s origin includes its transformation through multiple physical form factors. These material changes frequently include moving from a lot/wafer/die physical structure to a singulated die on a piece of tape or reel to an assembled die in a package, or in a tray, or as an inserted chip in a multi-chip module or PCB — ultimately ending with the PCB being inserted into a larger form factor, such as an automobile or a computer server. Each time the physical form factor is updated, there is a chance to break traceability in the supply chain if incoming and outgoing product labels are not meticulously documented. This is exacerbated by a lack of standardized data formats and communication frameworks throughout the supply chain. All too often, there is a gap in a unit’s back mapping. Once this occurs, any chance to trace a problem to a source is jeopardized.
It may surprise you, but when it comes to chips in electronic braking systems, airbag control units, and more, automotive manufacturers are still using 10-year-old technology — and with good reason.
For the automotive industry, the reliability, stability, and robustness of electronic components are critical, especially when it comes to meeting the stringent Automotive Electronics Council (AEC) Q100 standards that fabs need to follow. Some in the industry would not only rather keep using proven older chips over new ones, but they might even call for the construction of new fabs for older chips. In other words, tried and true is better than new and improved.
After TSMC announced plans to construct a new fab in Arizona, the Taiwan-based company disclosed that they are considering building new fabs in Japan and Germany. While the Arizona fab will focus on producing 5nm nodes using extreme ultraviolet lithography (EUV) technology, the new plant in Japan reportedly would focus on the 28nm node. This 28nm fab in Japan would be in addition to a 28nm fab expansion in China.
Given that the latter node was introduced in 2008 and is not regularly used today to build central processing units (CPU) and graphics processing units (GPU), the question arises, why is TSMC building not one, but three new fabs centered around 28nm node production? The answer is simple: customer demand.
And in this case, that demand is powered by devices and applications that use augmented reality (AR) and virtual reality (VR). Most of the devices, including those that use CMOS image sensors (CIS), are manufactured on 28nm to 80nm node technology. This is why major foundries, including TSMC and Samsung, are preparing to ramp up their volume production for these more mature nodes.
As a further illustration of the demand for the 28nm node, consider this: Apple is planning on manufacturing compact, high-resolution, micro organic light-emitting diode (OLED) display devices on silicon wafers, and Sony is planning on building image signal processing (ISP) devices; both companies will be using 28nm node technology.
AR overlays digital content and information onto images of the physical world captured by camera, and it is one of the biggest technology trends now. Apps like Snapchat and games like Pokémon GO first popularized AR, but the technology is predicted to become a part of our daily lives, influencing how we shop at brick-and-motor stores or drive (or not drive in the case of autonomous vehicles) our cars.
VR, meanwhile, is already widely used at work and home. While some gamers have embraced VR with a passion, advanced manufacturers regularly use VR to train employees. As for my company, Onto Innovation, we adopted and started using VR technology — in this case, Oculus from Facebook — for training and field support during the pandemic since some people could not meet face-to-face due to travel restrictions.
These incredible advancements in the use of AR and VR wouldn’t be possible without CIS. And with both AR and VR growing in popularity, there is no doubt that CIS applications will increase in the future.
The following paper presents a case study describing how to improve yield and fab productivity by implementing a frequent pattern database that utilizes Artificial Intelligence based Spatial Pattern Recognition (SPR) and wafer process history. This is important because associating spatial yield issues with process and tools is often performed as a reactive analysis, resulting in increased wafer scrap or die loss that could be prevented. The implementation of fab fingerprint technology proactively generates a pareto of high impacting process steps and tools based on a pattern score, enabling the production team to concentrate more efficiently on yield limiting events.
The demand for smartphone cameras, video conferencing, surveillance and autonomous driving has fueled explosive growth of CMOS image sensor (CIS) manufacturing in the last decade. While CIS becomes an increasingly important element in the production of today’s consumer electronics, there are unique challenges in production that must be addressed. As pixel sizes shrink, we see an inverse relationship with the number of pixels in the array increasing, which presents challenges for process control of the sensor, especially as it relates to the color filter array (CFA) and on-chip lens (OCL). With the push to 1µm and below pixel sizes, the ability to find sub-micron defects and macro-level variations within the pixel array is even more important to ensure uniform and unobstructed responses throughout the active pixel sensor array (APS).
CIS is unique from other semiconductor devices because it converts light energy into electrical signals. It is manufactured on silicon wafers similar to semiconductors and follows typical back-end packaging processes such as grinding, sawing, and electrical testing. A typical CIS device has an ASP region in the center of the die with electrical I/Os (bondpads) on the periphery. Deionized water is often used to clean up mobile contamination left behind during the wafer thinning or die singulation process which has an inherent risk of staining or leaving a residue on the APS that affects the quantization of light and is considered a killer or yield limiting defect.