EB40™ Module
The EB40 Module combines edge and backside inspection into one tool with the option to be paired with an inspection system to provide a high throughput all surface inspection solution.
Product Overview
The Class 1 certified EB40 module offers combined edge and backside inspection and is also available as separate edge (E40) and backside (B40) modules. These modules provide brightfield and darkfield inspection to detect defects on the entire bevel and backside, covering Zone 1 to Zone 5. This enables faster root-cause analysis of defects that can migrate to the wafer interior, impacting die yield.
The EB40 module captures defect images on the fly, creates whole-wafer composite images, and integrates with SEM bevel review. All inspection and metrology results, including defect, whole wafer and SEM images can be analyzed together in a single database using Discover Defect software. Correlating EBR metrology with defectivity data, SEM data and micro-inspection results is just the beginning of what Discover software can do. In addition to advanced on-tool defect binning, real-time edge ADC classification can be assigned to defects prior to manual offline review using Discover Review software.
Applications
- EDGE INSPECTION
- Lithography process monitoring
- Cracks/Chips, Slurry, cleaning contaminants and residual films
- EBR Metrology
- Bonded wafer adhesive inspection
- BACKSIDE INSEPCTION
- Scratches
- Chuck and end effector signatures
- Backside particles and residues
- Wafer level pattern detection
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Dragonfly® G3 System
The Dragonfly G3 system is resetting the industry’s expectations for throughput, accuracy and reliability. Combining 2D and 3D technologies, the system detects yield-robbing defects and measures features critical for today’s semiconductor technologies
Product Overview
The Dragonfly G3 is a widely adopted pattern inspection system that utilizes line scan imaging technology to deliver fast, sub-micron defect detection for both R&D and high volume manufacturing environments. It features multiple illumination channels, including brightfield, darkfield, high-speed IR for embedded defects, and Clearfind® technology for detecting non-visual organic residues. Powered by modern machine learning algorithms, the Dragonfly G3 system offers a complete on-tool solution for defect detection, nuisance reduction and classification.
The system offers additional flexibility through the integration of multiple 3D metrology capabilities, including film thickness and structural profiling, and substrate thickness measurement. It features the latest 3Di™ technology, delivering and precise bump height metrology. The Dragonfly G3 system, with optional edge and backside inspection via the EB40 module, offers a comprehensive all-surface inspection solution for both front-end and back-end OQA.
Applications
- Redistribution layers (RDL): after develop, after etch
- Reconstructed and bonded wafers
- Micro bumps and Cu pillars
- Post saw
- Gel and waffle pack inspection
- Post probe and testing
- OQA
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Hybrid Bonding Process Control Solution
Hybrid bonding enables ultra-dense 3D memory interconnects with up to 1,000x more connections than microbumps. Achieving high yield requires stringent process control, including monitoring topography and detecting particles, cracks and voids. Measuring dishing in copper pads provides valuable insight into surface conditions. Together, these process control insights contribute to improved device reliability and performance.
Enabling In-Line Process Control for Hybrid Bonding Applications
As demand grows for high-performance computing (HPC) and AI-driven applications, manufacturers are turning to hybrid bonding to enable the ultra-dense 3D integration required for next-generation chip architectures. This advanced packaging technology presents significant process challenges. Surface preparation must be precisely controlled to eliminate particles, excess recess, and copper pad dishing, all of which can compromise bond quality. During pre-annealing, particle-induced gaps and wide bonding gaps can prevent proper wafer contact. Post-annealing, the formation of dielectric and metal voids introduces further risks to electrical performance and long-term reliability.
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Abstract
A vital component of modern communication systems, bulk acoustic wave resonators (BAW) function as filters, oscillators, and sensors. In a BAW device, the acoustic waves are confined within a specific region to achieve efficient resonance. The air ring structure, including the edge air layer structure, prevents acoustic energy from leaking. However, measuring the critical dimensions (CD) of edge air layers is challenging. In this paper, we will show how Onto Innovation’s IVS™ 220 optical overlay and CD metrology system can measure the edge air layer structure using a CD step application. The IVS 220 system provides good repeatability and high throughput [130 wph, five (5) fields, one (1) site per field]. In addition, the IVS 220 system also can be used for overlay measurement, CD measurement (including angle CD and diameter of the circle or hole), and Z height measurement.
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Abstract
The bipolar-CMOS-DMOS (BCD) process is an advanced semiconductor technology integrating bipolar, CMOS, and DMOS devices onto a single chip, providing a compact, high-performance platform for the integration of analog, digital, and power circuitry. Thin-film resistors are employed to ensure precise resistance values and minimal temperature coefficients (TCR), thereby delivering enhanced accuracy and reliability for analog circuit applications. The SiCr thin-film resistor exhibits low TCR, consistent resistance values, minimal parasitic capacitance, and low leakage current. These characteristics surpass those of diffusion resistors, making SiCr thin-film resistor a good candidate for the precision resistance networks required in high-accuracy integrated and module circuits for BCD process. Picosecond ultrasonics (PULSE™ technology) has become a prevalent method in metal film measurement due to its rapid, contactless, and non-destructive capabilities. In this work, we demonstrate that picosecond ultrasonics has outstanding repeatability [1sigma<0.5Å] in SiCr thickness measurement as well as its excellent sensitivity to small thickness variations. SiCr thickness and uniformity could be well monitored and controlled. Furthermore, PULSE technology can reflect the surface quality of the film by measuring the probe beam (522nm) reflectivity. Then, specialty gases flow rate would be closely monitored and controlled to achieve target SiCr thin films with desirable TCR properties.
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Looking to learn more about our innovative solutions and capabilities? Our team of experts is ready to assist you. Reach out today and let’s starts a conversation about how we can help you achieve your goals.
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Semiconductor manufacturing creates a wealth of data – from materials, products, factory subsystems and equipment. But how do we best utilize that information to optimize processes and reach the goal of zero defect manufacturing?
This is a topic we first explored in our previous blog, “Achieving Zero Defect Manufacturing Part 1: Detect & Classify.” In it, we examined real-time defect classification at the defect, die and wafer level. In this blog, the second in our three-part series, we will discuss how to use root cause analysis to determine the source of defects. For starters, we will address the software tools needed to properly conduct root cause analysis for a faster understanding of visual, non-visual and latent defect sources.
Whether the discussion is about smart manufacturing or digital transformation, one of the biggest conversations in the semiconductor industry today centers on the tremendous amount of data fabs collect and how they utilize that data.
While chip makers are accumulating petabytes of data across the entire semiconductor process, a question arises: how much of that information is being fully utilized? The answer may be around 20%, according to the Semiconductor Engineering article “Too Much Fab and Test Data, Low Utilization.” Unfortunately, this poses a challenge because fab end customers are demanding highly reliable chips, in other words, chips with zero escaping defects and which offer manufacturers clear genealogy and traceability.
Many of you reading this work for companies that have started or are planning digital transformations. To do this, these companies will need to better integrate the data they collect — and that includes data from materials, products, processes, factory subsystems and equipment.
For smart manufacturing to truly live up to its potential, manufacturers will need inline automation that takes complete advantage of the analytics their monitoring systems generate, analytics which can be fed back to the process tools, manufacturing execution systems and other factory systems in real time. Working in concert, these integrated systems are essential to creating a zero defect manufacturing environment.
In the world of smart manufacturing, manufacturers will be tasked with providing timely total solutions to detect and classify defects using inspection and metrology tools, conduct root cause analysis to determine the source of said defects and, finally, employ process control and equipment monitoring using run-to-run and fault detection and classification software solutions to prevent defects from reoccurring.
In this blog, the first in our three-part series “Achieving Zero Defect Manufacturing,” we will focus on detecting and classifying defects. We will start by looking at solutions at the defect level before moving on to the die level and the wafer level.