The primary application of non-contact CV metrology is monitoring dielectric properties during IC manufacturing. Unlike conventional electrical measurements, it requires no sample preparation, eliminating the need for MOS capacitor structures. This reduces metrology cost and enables fast data feedback in both R&D and manufacturing environments. 

The corona-Kelvin method uses a corona discharge in air to deposit an electric charge (DQC) on the wafer surface. A vibrating Kelvin-probe then measures the resulting surface voltage (V), enabling determination of the differential capacitance (C= DQC/DV). By monitoring surface voltage in both dark and illuminated conditions, the system separates two key components: dielectric voltage (VD) and semiconductor surface potential (VSB), enabling determination of flat band voltage (VFB). 

Analysis of the resulting charge-voltage data yields electrical parameters, including trap density (Dit), flat band voltage (Vfb), dielectric charge (Qtot), dielectric capacitance (CD), Equivalent Oxide Thickness (EOT), leakage current, and tunneling characteristics. 

As more high aspect ratio processes are used in multiple industry segments, there are metrology needs for monitoring of related processes, including dimensions and properties of carbon film hard masks and etched 3D structures. 

The MBIR system delivers high-throughput, low COO, non-contact, non-destructive measurements of dimensions and uniformity of layers and etched structures used in integrated circuit manufacturing. The small spot size makes the tool suitable for measurements of scribe line test structures as in-line process control. The unique technology and analysis capability simplifies system calibration requirements and removes the effect of substrate variations for key layer measurements.  

While the software contains advanced features for measurement recipe and analysis model creation, it has a user-friendly interface and implementation that allows the fab customers to create and manage the recipe system for MBIR tool fleets. 

Thickness map from amorphous carbon film

There is no disputing the detrimental effect of metallic contamination on the integrity of the critical gate oxide used in integrated circuits. During high temperature processing, contamination in the silicon wafer often precipitates at the Si/dielectric interface or segregates into the dielectric—both scenarios can cause premature device failure and reduced yield. As device dimensions shrink, the tolerance for contamination decreases, requiring ever-lower background levels of metals like iron (Fe). Over the past 25 years, the IC industry has reduced typical Fe concentrations by more than three orders of magnitude, yet further reduction is essential, especially for applications like CMOS image sensors. 

The FAaST Digital SPV system addresses this challenge with industry-leading sensitivity and speed. It provides a fast, non-contact, and preparation-free method for full-wafer imaging of contamination. High-resolution maps of minority carrier diffusion length and Fe concentration are generated in minutes, enabling fabs to detect and control contamination at levels as low as the E7 cm⁻³ range. 

Figure 1. Typical background Fe concentration in new IC Fablines (blue) and the state-of-the-art SPV detection limit (red)

The CnCV system utilizes a novel constant surface potential corona charging, which enables the precision required over a large voltage range. The patented technology includes charge- and photo-assisted modes, especially suited for speed and precision on WBG materials and structures, including SiC, Ga2O3, GaN, and AlGaN/GaN HEMT. Additionally, Corona-Kelvin characterization includes electrical properties of dielectrics and interfaces of films on SiC and GaN epi layers. An automated top-side edge contact (TSEC) is also available enabling characterization of WBG on insulating/semi-insulating substrates. Automated bias-temperature stress (BTS) measurements are also available with the CnCV system, providing a fast, noncontact way to quantify the reliability of passivated SiC and GaN. 

Beyond typical CV type parameters, the full wafer corona approach allows for QUAD (quality, uniformity, and defect) mapping. The electrical defect imaging, QUAD-EDI, mode is especially designed for SiC. It provides a unique means for quick screening of epi electrical defectivity enabling improvement in device yield prediction. 

Figure 1. QUAD-EDI Map on final metallized device wafer after Merged Schottky PiN diode fabrication identifying failed dies.

As semiconductor manufacturers push into next-generation GAA nodes and next-gen HBM and vertical DRAM architectures, process control requirements are tightening. Smaller nanosheet structures and denser DRAM cells demand higher measurement precision, faster recipe development, and tighter tool-to-tool matching.

The Atlas® G6 system is engineered to meet these challenges with a new optics design that improves signal-to-noise ratio, spectral stability, and measurement precision. Enhanced software algorithms and data management tools deliver better fleet-wide spectra matching, while a new data channel and next-generation model-guided machine learning in Ai Diffract™ software enable faster, more robust recipe development. A smaller optical spot size ensures accurate measurements on today’s most compact DRAM structures.

Fully integrated with Onto Innovation’s Discover® ecosystem, the Atlas G6 system empowers fabs with predictive process control and smart manufacturing capabilities—accelerating yield and time to market for the industry’s most advanced devices.