Onto Innovation’s Doug Brown is pleased to publish, “The Great Lithography Debate: Copper Clad Laminate or Glass Substrates?” in the January-February 2024 issue of the Chip Scale Review.

It is no mystery that the semiconductor industry is always advancing, with specifications becoming increasingly stringent as defects become increasingly more difficult to discover. This is especially true in the case of the most advanced nodes, where ever-smaller flaws and deformities can result in a killer defect.

To solve this More than Moore mystery, you do not need to employ the detective skills of Sherlock Holmes. You need the metaphorical equivalent of the pipe-smoking hero’s magnifying glass to find the particles, scratches, pits and air pockets hiding in the shadows.

Take the critical dimensions of trenches and vias, for example. As they shrink, the size of a particle or scratch that can potentially result in a killer defect decreases in size as well, making sensitivity an increased priority for bare wafer inspection — on the frontside and backside, at the edge and in the notch.

With an eye on evolving requirements for advanced node bare wafers, manufacturers are seeking inspection solutions with automatic defect classification (ADC) capabilities to perform outgoing quality assurance for wafers, including polished wafers and those with silicon epitaxial layers. Armed with these ADC capabilities, customers can significantly reduce the need for time-consuming and costly manual review.

The frontside, bulk, backside, edge and notch — each of these areas needs to be inspected to ensure the quality of the silicon wafer and the successful fabrication of advanced devices on the wafer. We’ll start with frontside and bulk before moving onto backside, edge and notch inspection, the main focus of this blog.

Faster data transfer, greater heat dissipation, less power consumption and increased functionality are all qualities that chipmakers and their customers want from their devices. Since the dawn of the semiconductor industry, the pursuit of increasingly advanced nodes has served as the industry’s North Star. But for today’s voyagers, rough seas are ahead: these nodes have decreased in size, input/output (I/O) bumps on the chip have grown smaller—and with the shrinking of these bumps, their ability to mate directly to printed circuit boards (PCB) diminishes. The way to avoid this is to use advanced IC substrate (AICS), i.e., an intermediary substrate that enables progress in panel-level packaging (PLP) and chiplets.

Chiplets are a type of advanced packaging in which multiple die—such as memory, analog and other devices— are assembled in a single, large package along with a central processing unit (CPU) or graphics processing unit (GPU). With AICS, all of these chiplets can be co-packaged together in packages that may be as large as 120mm x 120mm each, which is a considerable increase from the 10mm x 10mm-sized packages of fan-out panel – level packaging (FOPLP). These large packages allow multiple die with smaller interconnects to be assembled and then redirected to larger contact bumps compatible with a PCB. None of this means the industry has left the pursuit of next-generation advanced nodes behind, or smaller packages for that matter.

Although the semiconductor industry has turned to chiplets and other advances to meet various next level performance needs and spur new innovations, advanced nodes remain key areas of development and advancement. But this move toward extra-large AICS packages signals the need for large exposure field, fine-resolution panel-level lithography systems that can expose entire panels using fewer exposures. The journey to a new era of chiplets and PLP, however, is fraught with challenges that must be overcome, including total overlay shift, yield loss and copper-clad laminate (CCL) substrate distortion. In this article, we will focus on these three challenges to the rapidly growing AICS market and outline several solutions that we have determined will enable manufacturers to address them.

“When will glass replace copper clad laminate on advanced IC substrates?”

That’s a question many on the heterogeneous integration (HI) side of the semiconductor industry are asking. Unfortunately, the answer is not straightforward.

But before we get to answering that, let’s take an advanced IC substrate (AICS) refresher. In other words, how did we get to the point where glass substrates have become a topic of discussion?

AICS provides a means to connect chiplets and passives with extremely high I/O count to the printed circuit board (PCB). In the process, AICS has facilitated a paradigm shift in packaging technology with the introduction of HI. This revolutionary approach to packaging provides a significantly cheaper alternative to silicon interposer technology, which is limited in the package sizes it can support.

The AICS is built around a fiberglass resin core with copper on both sides. This is known as copper clad laminate (CCL). The CCL facilitates the creation of redistribution layers (RDL) that connect through the substrate core with plated through holes (PTH). The RDLs are separated by organic dielectric layers known as build-up films.