By Marshall Wilson
Abstract
Noninvasive, wafer-level electrical characterization enabled by the corona-based noncontact capacitance–voltage (CnCV) technique has gained significant attention since its introduction in 2018 as a cost- and time-efficient solution for wide-bandgap (WBG) semiconductor development and manufacturing. Using the CnCV® system, a controlled charge (ΔQ) is deposited on the wafer surface via corona charging, establishing an electrical bias. The resulting surface potential response (ΔV), measured using a vibrating Kelvin probe, enables extraction of differential capacitance (C = ΔQ/ΔV) and full CV characteristics without the need for fabricated test structures, gates, or metal contacts. The technique has demonstrated robust capability across SiC, GaN, Ga₂O₃, and AlGaN/GaN HEMT structures, including dopant profiling and 2DEG characterization, and has emerged as a clean, mercury-free alternative to conventional mercury probe CV (MCV).
CnCV has been continually evolving with major objectives of enhancing wafer throughput and reducing edge exclusion. A key innovation in state-of-the-art CnCV tools is the introduction in 2025 of illumination-induced charge pulsing, enabling a new “Kinetic mode” of operation that provides high measurement speed, enhanced precision and resolution. In this mode, millisecond duration illumination pulses can be as much as two orders of magnitude shorter than standard incremental corona charging resulting in an approximately 10x improvement in measurement speed. In addition, the technique enables reduced edge exclusion down to 3mm, increasing the effective measurement area on the wafer which is an important advantage for both development and manufacturing environments.
Equivalence between illumination-induced charge pulsing kinetic mode and traditional corona charging has been experimentally validated through direct comparison of CV characteristics and extracted dopant profiles. Near 1:1 agreement is demonstrated on 200 mm n-type 4H-SiC wafers in Fig. 1, confirming the accuracy of the kinetic approach.
The benefits of kinetic mode are particularly impactful for wafer-level electrical parameter mapping. For example, full-wafer mapping of AlGaN/GaN HEMT structures with 49 measurement sites can now be completed in approximately 8 minutes, compared to ~40 minutes using conventional CV methods. This enables practical, high density spatial characterization of critical electrical parameters previously limited by throughput constraints.
Application of this technique to AlGaN/GaN HEMT wafers enables simultaneous mapping of key electrical parameters, including two-dimensional electron gas (2DEG) sheet density (NS), pinch-off voltage (VP), and electrical AlGaN barrier thickness. Such mapping can be uniquely beneficial for establishing the process dependence of HEMT parameters and the correlation between different parameters. For example, wafer scale mapping of an AlGaN/GaN HEMT structure in Fig. 2 shows that uniform AlGaN thickness and Al composition do not guarantee uniformity in NS and VP, revealing significant electrical variation despite tight epitaxial thickness control. This highlights the importance of direct electrical characterization and the value of multi-parameter wafer mapping. A single wafer measurement thus provides data equivalent to multiple discrete test structures, significantly accelerating process development and optimization.
In conclusion, the latest CnCV advancements, including the new kinetic mode operation, demonstrate performance that matches or surpasses conventional electrical metrologies while providing unique advantages: true noncontact measurement, elimination of mercury and contamination risk, no requirement for test structures, significantly higher throughput, expanded measurable wafer area through reduced edge exclusion, and the ability to generate spatially resolved, multi-parameter datasets from a single wafer. These capabilities position CnCV as a state-of-the-art metrology platform for WBG materials, enabling faster development cycles, improved process control, and more direct correlation to device level performance.
Event Details
| Date | Oct 26, 2026 |
|---|---|
| Time | 2:30 pm — 5:00 pm |
| Location | Calgary, Canada |
| Event | 250th ECS Meeting |
| Room | 235 (Level 2, BMO) |
| Presenters |