The growing demand for heterogeneous integration is driven by the 5G market that includes smartphones, data centers, servers, HPC, AI and IoT applications. Next-generation packaging technologies require tighter overlay to accommodate a larger package size with finer pitch chip interconnects on large format flexible panels.
Fan-out panel level packaging (FOPLP) is one of the technologies that is able to achieve market requirements, but also faces several signification processes challenges. One critical challenge for FOPLP is die placement error, which is a result of the reconstitution process. Die placement error can cause high overlay error, which induces low overlay yield. To address this situation, site by site correction exposure with feedforward lithography is proposed. Site by site correction exposure can overcome the die placement error to achieve an acceptable overlay yield, and feedforward lithography is used to improve the throughput when using site by site correction exposure. An issue was observed when using feedforward site by site correction method: when one or more reconstituted dies suffered large displacement error, these large error dies affect the correctable accuracy of the site and induce poor overlay to all the dies in the site. To address this issue, which could induce poor overlay, advanced outlier control technology is proposed. Advanced outlier control technology is used for identifying the large error dies and processing these large error dies to prevent the situation.
In this paper, we demonstrated advanced outlier control technology with feedforward lithography on a selected test vehicle, which is a 510 mm x 515 mm panel. 400 simulation dies were built on this panel and part of the dies were designed with a large displacement error. The panel was processed using advanced outlier control technology with feedforward lithography in the demonstration. This demonstration showed how these two technologies integrated together and how this integration strategy worked for the FOPLP process. We also review and discuss the results for how this integration technology can maintain yield and throughput under such challenging conditions.
The growing demand for heterogeneous integration is driven by the 5G market that includes smartphones, data centers, servers, HPC, AI and IoT applications. Next-generation packaging technologies require tighter overlay to accommodate a larger package size with finer pitch chip interconnects on large format flexible panels.
Heterogeneous integration enables next-generation device performance gains by combining multiple silicon nodes and designs inside one package. The package size is expected to grow significantly, increasing to 75 x 75 mm and 150 x 150 mm, within the next few years. For these requirements, an extremely large exposure field with fine resolution lithography will enable packages well over 250 x 250 mm without the need for image stitching while exceeding aggressive overlay and critical uniformity requirements for these packages.
The lithography challenge to fulfill the need of heterogeneous integration is the limitation of exposure field size of the currently available solutions in the market. Multiple shots with stitching is used and this affects not only productivity performance but potential yield loss at the stitching boundary. Addressing the critical lithography challenges described above becomes an important task in heterogeneous integration, and an extremely large exposure field with fine resolution lithography is one of the best solutions for this task.
In this paper, a 515 mm x 510 mm panel is selected as the test vehicle, and we will demonstrate an extremely large exposure field with fine resolution technology on this panel. This demonstration provides the results and details about how this new technology will address the challenges of large package size processes.
The following paper presents a case study describing how to improve yield and fab productivity by implementing a frequent pattern database that utilizes Artificial Intelligence based Spatial Pattern Recognition (SPR) and wafer process history. This is important because associating spatial yield issues with process and tools is often performed as a reactive analysis, resulting in increased wafer scrap or die loss that could be prevented. The implementation of fab fingerprint technology proactively generates a pareto of high impacting process steps and tools based on a pattern score, enabling the production team to concentrate more efficiently on yield limiting events.
Optically opaque materials present a series of challenges for alignment and overlay in the semi-damascene process flow or after the processing of the magnetic tunnel junction (MTJ) of a Magnetic Random-Access Memory (MRAM). The overlay and alignment of a lithographically defined pattern on top of the pattern and the underlying layer is fundamental to device operation in all multi-layer patterned process flows. There are a wide variety of optical techniques and specially designed targets (Figure 2) that are used to address this problem in conventional flows. Typically, either an ultraviolet, visible, or infrared light is coupled through the top photoresist layer or an etched hard mask to be aligned to the bottom layer [1]. However, in some MRAM flows this coupling may not be possible as there may be an intervening opaque layer (Figure 1). In such cases, conventional methods of alignment using light fail. To overcome this issue, extra patterning operations may be used to open areas around the alignment features, but these operations add significant process cost.
In this paper we evaluate the use of picosecond laser acoustics (PLA) measurement as an alternative method to characterize the overlay and alignment patterns that are embedded under opaque metal films. We selected the MRAM process flow for this study where the different overlay and alignment markers were underneath opaque layers including an MTJ layer. These specific markers are imaged with the help of PLA employing an ultrafast laser in a pump and probe configuration to generate and detect acoustic waves capable of propagating through optically opaque layers. This technique, in sharp contrast with other competing acoustic imaging techniques such as scanning acoustic microscopy (SAM) [5,6], does not require the sample to be submerged in a coupling medium such as water.
Picosecond Ultrasonics (PULSE Technology) has been widely adopted as the tool-of-record for metal film thickness metrology in semiconductor fabs around the world. It provides unique advantages, such as being a rapid, non-contact, non-destructive technology, and has capabilities for simultaneous multiple layer measurement. In this paper, we describe the unique advantages of Picosecond Ultrasonics for advanced radio frequency (RF) applications. RF filter process control requires stringent metrology due to tight process tolerances. The first principles-based PULSE technology does not require external calibration standards and provides robust measurement capability for multi-layer thickness measurements. For advanced RF applications, the capability of PULSE technology to measure both velocity and thickness simultaneously for transparent and semi-transparent films offers a lot of potential for not only monitoring processes but offers insight into the device performance. The PULSE technique can also simultaneously measure full stack for multilayer metal stack measurements with excellent repeatability and long-term stability which makes process control more efficient and reliable. Fast throughput makes it possible for a high sampling rate for RF applications which is the key for device level process control and yield improvement.
The global RF semiconductor market size is growing rapidly at a CAGR of 8.5% in the next five years from 17.4 billion in 2020 to 26.2 billion USD in 2025. The rollout of 5G technology and its enabled Internet of Things (IoT) are the main driving force for this growth. Each 5G device requires up to 100 filters to make sure each band is isolated to avoid interference that will drain battery life, reduce data speeds, and cause dropped calls. RF filters are becoming more and more critical for all signal process applications. 5G devices require Bulk Acoustic Wave (BAW) filters which can work better at higher frequencies. With more and more filters to fit into a device, the size of filters is also shrinking dramatically in three dimensions. These advances in filter technology place stringent demands on manufacturing which in turn requires accurate and precise metrology techniques. Both thickness and acoustic properties of the piezoelectric layer determine the frequency response of filters. Thickness accuracy and uniformity requirements for the films are beyond what process tools can offer at deposition and there are several options available to achieve such tight controls post-deposition. Metrology techniques employed for characterizing these properties must meet the sensitivity, accuracy, and stringent repeatability requirements. The thickness of the full stack and especially the thickness and sound velocity of the piezoelectric layer are key to realizing the extremely tight process control of frequency accuracy (3σ) of 0.1% or better. A high sampling rate on a hundred-micron level device is needed to make sure all devices across the wafer can meet the requirements which require fast throughput with a small measurement probe.
Fan-out wafer level packaging (FOWLP) is a popular new packaging technology that allows the user to increase I/O in a smaller IC size than fan-in wafer level packaging. Market drivers such as 5G, IoT, mobile and AI will all use this technology. According to Yole Développement’s analysis, the fan-out packaging market size will increase to $3 billion in 2022 from $2.44 hundred million in 2014, validating the market requirement for fan out packaging. While FOWLP has been used for many years, there is still a relentless drive to reduce the cost, and fan-out panel level packaging (FOPLP) has been proposed as one possible solution. FOPLP allows users to put more chips on a substrate, meaning more product output and a higher substrate utilization percentage. According to Yole’s analysis, the FOPLP market size will increase to $2.79 hundred million with 79% CAGR, showing that more people are adopting FOPLP.
FOPLP has many advantages and low cost potential, but it faces significant process challenges, such as die placement error and substrate warpage control. One of the key challenges is the trade-off between overlay, yield, and throughput during the lithography processing steps. A user exposes multiple dies per exposure shot to increase throughput, but this can result in lower overlay yield because of “pick and place” die placement error. To overcome the low yield issue, each die needs to be aligned, but this impacts throughput, so a compromise is required. To find the balance point between throughput and overlay is one of the biggest challenges for FOPLP.
In this paper we address the tradeoff between throughputs and overlay yield, we demonstrate an integrated feedforward adaptive shot solution. This feedforward approach uses a third party metrology system to measure reconstituted panel die location data and sends the data to the stepper via a network. With feedforward algorithm technology, the stepper uses smart adaptive shot technology to generate an optimized variable shot size layout. This layout ensures the overlay yield is within specification with the minimum number of exposure steps. With feedforward adaptive shot technology, the user can maximize the throughput of the stepper and ensure the overlay yield at the same time.
Key words: advanced packaging, die placement error, FOWLP, FOPLP, overlay, yield, feedforward.