Abstract
Surface Relief Grating (SRG) waveguides have been adopted as the mainstream solution in the industry, for its slim profile, high transparency, and large field of view. Furthermore, with their superior optical performance and mass production potential, SRG waveguides have emerged as a critical pathway for high‑performance augmented reality (AR) and mixed reality (MR) displays. In the mass production of SRG optical waveguides, where multi‑layer and double‑sided fabrication demand strict process control of overlay, geometry, and defects. We present a full process control solution for SRG mass production, combining optical critical dimension (OCD) metrology for the critical parameters of SRGs such as the grating depth, slanted angle, and periods, picosecond ultrasonic (PULSE™) technology for the metal film thickness measurement, image‑based overlay (IBO) on the IVS™ platform for precise overlay control, automated optical inspection based Dragonfly® system for the defects integrated throughout the entire SRG manufacturing process. OCD shows sub‑nanometer deviation and excellent matching with AFM, with high dynamic stability. PULSE™ technology ensures rapid, non‑contact measurement and uniformity control of chromium (Cr) and aluminum (Al) hard masks. Overlay precision reaches 0.26 nm (X) and 0.18 nm (Y) at 3σ, well within sub‑100 nm alignment requirements. Automated inspection captures >95% of submicron defects with low false positives. This framework has been validated in mass production at leading AR/MR manufacturers, enabling fully digitalized closed‑loop process control and supporting large‑scale, high‑yield SRG waveguide manufacturing.
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Abstract
In this review we discuss two recent CnCV metrology advancements, namely: 1. enhancement of throughput and 2. use of electrical defect mapping for yield prediction. Novel 10x faster measurements of critical WBG semiconductor electrical parameters are based on the discovery of a linear UV radiation induced electrical charge biasing. Example results for an AlGaN/GaN HEMT structure illustrate wafer uniformity mapping reduced from hours to minutes and enabling the prediction of the useful wafer area. The second development on SiC device yield was realized as a joint project with Nexperia and Fraunhofer IISB in Germany [2]. The project took advantage of the unique electrical defect mapping capability of the QUAD (Quality, Uniformity and Defect) technique in CnCV tools. Macro and micro-scale QUAD mapping applied to a merged PiN Schottky (MPS) diode manufacturing process correlated QUAD bin map results with failed dies identifying the culprit epi-layer and process induced defects. This development paves a realistic path for meeting the demand for more advanced electrical defect detection and improving device yield prediction.
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Abstract
AI chiplet architectures are driving advanced IC substrates (AICS) toward larger panels, finer line/space, and much tighter overlay budgets. This study presents a lithography strategy that combines ultra-large exposure field and fine-resolution imaging with algorithmic early zone correction (EZC) to reduce alignment-solution errors, the largest item in the lithography overlay budget. In this study, we use overlay data from 510 x 515mm panel test vehicles to identify zone-level correctables and apply in-exposure pre-compensation. The approach reduces overlay errors in high-volume manufacturing, improving overlay by 38.2%. The methodology generalizes to ultra-high-density fan-out and 2.5D/3D packaging, providing a practical path to sustain overlay yield for next-generation AICS.
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Abstract
In traditional semiconductor packaging, manual defect review after automated optical inspection (AOI) is an arduous task for operators and engineers, involving review of both good and bad die. It is hard to avoid human errors when reviewing millions of defect images every day, and as a result, underkill or overkill of die can occur. Automatic defect classification (ADC) can reduce the number of defect images that need to be reviewed by operators. The ADC process can also be integrated with AOI engines to reduce nuisance defect images to reduce AOI image capturing time. This paper will focus on how to utilize Onto Innovation’s TrueADC software product to build ADC classifiers using a multi-engine (ME) solution. The software supports CNN, DNN and KNN algorithms. The use of CNN and DNN are currently mainstream in the development of deep learning (DL) for ADC classification in the semiconductor industry. We will address how to improve classification by using multiple models in the classification process with unique algorithms. As a result, the user can achieve industry requirements with very demanding specifications, like high accuracy, high purity, and high classification rate with very low escape rates.
Abstract
DRAM storage node profile measurement during high aspect ratio (HAR) etch has been one of the most challenging metrology steps. DRAM storage node profile affects refresh time and device electric quality. So, controlling this profile is one of the key challenges. Conventional 3D modeling in Optical Critical Dimension (OCD) metrology has typically used multiple cylinder stacks. This method cannot provide an accurate model and computed spectrum through the RCWA engine. This means we need a more accurate model. In this paper, we used hyper-profile to accurately measure a hole profile for better process control. Hyper-profile uses a polynomial to describe the smooth shape of a hole profile, which is much closer to the real product and provides a more accurate computed spectrum. With hyper -profile, a continuous storage node hole profile and managed CD correlation are achieved. It can maintain the same profile complexity with less degree of freedom, reducing the model uncertainty and ensuring more robust regression. On the other hand, as the metrology error budget becomes stricter and the process variation cycle is increasing, the OCD based model-guided machine learning (MGML) approach can provide a faster solution turnaround time with more accurate measurements than either pure OCD or pure ML approaches. It also can better decorrelate profile CDs and achieve more robust profile monitoring. In this paper, we will demonstrate the above benefits of hyper -profile and MGML in the DRAM storage node application.
What is 4D InSpec?
A handheld, 3D surface measuring gauge. It takes a measurement in about 1-2 seconds, in-situ. It’s highly accurate, with micron-level precision. The instrument was first used for measuring defects on precision machined parts. It quickly assesses scratches, pits, nicks, corrosion and other defects, and assures the quality of features like peening, scribe marks, edge blending and rivets. Its analysis software measures and quantifies edge break, radius of curvature with high precision. It’s easily set up for pass-fail analysis. 4D InSpec improves profitability in repair and new-make manufacturing processes in the aviation, automotive, nuclear and general precision machining sectors.
Why
Consider your highest-value part. If you could reduce the number of those that are
scrapped or reworked via inaccurate inspection by 40%, how much money would that save you?
What
The 4D InSpec surface measuring gauge produces fast, numerical, objective surface
information needed to assess components. By quantifying quickly and easily, customers have reported a 20-40% increase in yield.
Who & Where
The instrument instantly reports defect statistics on precision machined
parts, and is transforming throughput in the MRO process for the aviation, automotive and nuclear energy industries. It is also used in industries as diverse as furniture, cutting tools, saw blade, and solar tile manufacturing.
Benefits
• High precision, quantified measurements increase yield by saving more parts
• Return on investment is normally days to weeks
• Records reliable, repeatable results you can share to prove your outcomes
• Reduces labor by saving on dismantling and part transportation
• Improves turnaround time by eliminating waiting, increasing throughput
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