Abstract
AI chiplet architectures are driving advanced IC substrates (AICS) toward larger panels, finer line/space, and much tighter overlay budgets. This study presents a lithography strategy that combines ultra-large exposure field and fine-resolution imaging with algorithmic early zone correction (EZC) to reduce alignment-solution errors, the largest item in the lithography overlay budget. In this study, we use overlay data from 510 x 515mm panel test vehicles to identify zone-level correctables and apply in-exposure pre-compensation. The approach reduces overlay errors in high-volume manufacturing, improving overlay by 38.2%. The methodology generalizes to ultra-high-density fan-out and 2.5D/3D packaging, providing a practical path to sustain overlay yield for next-generation AICS.
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Abstract
In traditional semiconductor packaging, manual defect review after automated optical inspection (AOI) is an arduous task for operators and engineers, involving review of both good and bad die. It is hard to avoid human errors when reviewing millions of defect images every day, and as a result, underkill or overkill of die can occur. Automatic defect classification (ADC) can reduce the number of defect images that need to be reviewed by operators. The ADC process can also be integrated with AOI engines to reduce nuisance defect images to reduce AOI image capturing time. This paper will focus on how to utilize Onto Innovation’s TrueADC software product to build ADC classifiers using a multi-engine (ME) solution. The software supports CNN, DNN and KNN algorithms. The use of CNN and DNN are currently mainstream in the development of deep learning (DL) for ADC classification in the semiconductor industry. We will address how to improve classification by using multiple models in the classification process with unique algorithms. As a result, the user can achieve industry requirements with very demanding specifications, like high accuracy, high purity, and high classification rate with very low escape rates.
Abstract
DRAM storage node profile measurement during high aspect ratio (HAR) etch has been one of the most challenging metrology steps. DRAM storage node profile affects refresh time and device electric quality. So, controlling this profile is one of the key challenges. Conventional 3D modeling in Optical Critical Dimension (OCD) metrology has typically used multiple cylinder stacks. This method cannot provide an accurate model and computed spectrum through the RCWA engine. This means we need a more accurate model. In this paper, we used hyper-profile to accurately measure a hole profile for better process control. Hyper-profile uses a polynomial to describe the smooth shape of a hole profile, which is much closer to the real product and provides a more accurate computed spectrum. With hyper -profile, a continuous storage node hole profile and managed CD correlation are achieved. It can maintain the same profile complexity with less degree of freedom, reducing the model uncertainty and ensuring more robust regression. On the other hand, as the metrology error budget becomes stricter and the process variation cycle is increasing, the OCD based model-guided machine learning (MGML) approach can provide a faster solution turnaround time with more accurate measurements than either pure OCD or pure ML approaches. It also can better decorrelate profile CDs and achieve more robust profile monitoring. In this paper, we will demonstrate the above benefits of hyper -profile and MGML in the DRAM storage node application.
What is 4D InSpec?
A handheld, 3D surface measuring gauge. It takes a measurement in about 1-2 seconds, in-situ. It’s highly accurate, with micron-level precision. The instrument was first used for measuring defects on precision machined parts. It quickly assesses scratches, pits, nicks, corrosion and other defects, and assures the quality of features like peening, scribe marks, edge blending and rivets. Its analysis software measures and quantifies edge break, radius of curvature with high precision. It’s easily set up for pass-fail analysis. 4D InSpec improves profitability in repair and new-make manufacturing processes in the aviation, automotive, nuclear and general precision machining sectors.
Why
Consider your highest-value part. If you could reduce the number of those that are
scrapped or reworked via inaccurate inspection by 40%, how much money would that save you?
What
The 4D InSpec surface measuring gauge produces fast, numerical, objective surface
information needed to assess components. By quantifying quickly and easily, customers have reported a 20-40% increase in yield.
Who & Where
The instrument instantly reports defect statistics on precision machined
parts, and is transforming throughput in the MRO process for the aviation, automotive and nuclear energy industries. It is also used in industries as diverse as furniture, cutting tools, saw blade, and solar tile manufacturing.
Benefits
• High precision, quantified measurements increase yield by saving more parts
• Return on investment is normally days to weeks
• Records reliable, repeatable results you can share to prove your outcomes
• Reduces labor by saving on dismantling and part transportation
• Improves turnaround time by eliminating waiting, increasing throughput
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In industries such as aircraft engines automotive, companies need to rapidly establish the quality of components, both during production and during repair and overhaul. Many of these components are highly valuable and complex, often with hundreds of features requiring inspection.
To date, much of this inspection has been completed manually—a slow and subjective process. A new, automated system is now being adopted for rapid, repeatable, non-contact measurement of features and defects on precision machined parts. Combining the flexibility of an industry-proven optical gage and
robotic automation, the system dramatically improves inspection throughput and reliability, recording quantitative data that can be tracked throughout the component’s lifetime.
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Abstract
The growing demand for heterogeneous integration is driven by the 5G market. This includes smartphones, data centers, servers, high-performance computing (HPC), artificial intelligence (AI) and internet of things (IoT) applications. Next-generation packaging technologies require tighter overlay to accommodate larger package sizes with fine-pitch chip interconnects on large-format flexible panels. Heterogeneous integration enables device performance gains by combining multiple silicon nodes and designs inside one package. The package size is expected to grow significantly, increasing to 75mm x 75mm and 150mm x 150mm, within the next few years. For these requirements, an extremely large exposure field fine-resolution lithography solution was proposed to enable packages well over 250mm x 250mm without the need for image stitching, while exceeding the overlay and critical uniformity requirements for these packages.
One of the challenges of extremely large exposure field fine-resolution lithography is to achieve an aggressive overlay number. Formation changes experienced by the panel as a result of thermo, high-pressure and other fan-out processes shift the design location from nominal coordinates; this causes inaccurate overlay and low-overlay yield in the lithography process. Addressing this critical lithography challenge becomes an important task in heterogeneous integration.
In this paper, a 515mm x 510mm Ajinomoto build-up film (ABF)+copper clad laminate (CCL) substrate is selected as the test vehicle. We will analyze the pattern distortion of an ABF+CCL substrate to understand the distribution of translation, rotation, scale, magnification, trap, orthogonality and other errors in the substrate, and then use extremely large exposure field fine-resolution lithography to address the pattern distortion of the substrate. This demonstration will provide an analysis of panel distortion and detail how the extremely large exposure field fine-resolution lithography solution addresses panel distortion to achieve an aggressive overlay number.