The ability to trace the genealogy of all the components in an electronic device has been getting more complex for decades. For many industries — automotive, defense, medical and others — the need to locate the source of a problem in near real-time is paramount to gauging the extent of that problem. The extreme case is when the issue occurs with a product that already has been distributed and used in the field. Complicating matters is the fact that the current chip shortage is pushing chip designers to second- and third-tier suppliers for their inventory.
Tracking information is not easily done given the number of times material can change hands during the manufacturing life cycle. Designs can incorporate IP modules from Parties No. 1, No. 2, and No. 3 (figure 1). These designs are blended into a singular chip by the device’s Design House. This chip is then built at Front-end Foundries No. 1 or No. 2. The completed chip can be tested and partially assembled at OSAT A, B, or C. Finished assembly into a multi-chip module (MCM) or printed circuit board (PCB) can take place at Assembly House No. 1 or No. 2 (or happen at Customer A if they provide the IP for a design for a device that can be assembled by Finished Goods Maker No. 1) before it is finally sold by the Design House to the End User or Final Goods Manufacturer A, B, C, D and more for insertion in their end product, after which it is again tested before being sold to the end customer.
This is a very simplified example of how complex a supply chain can be, but it is illustrative nonetheless.
Virtual v. physical traceability
At some point in the supply chain, units receive a physical marker that enables traceability as it progresses through the remaining chain of manufacturing agents. Prior to the application of a marker, reliance on a part’s origin is a function of accounting and accurate recordkeeping. Although this seems simple enough, it is complicated by the transition of “ownership” of the chip as it moves through the supply chain.
Tracing a chip’s origin includes its transformation through multiple physical form factors. These material changes frequently include moving from a lot/wafer/die physical structure to a singulated die on a piece of tape or reel to an assembled die in a package, or in a tray, or as an inserted chip in a multi-chip module or PCB — ultimately ending with the PCB being inserted into a larger form factor, such as an automobile or a computer server. Each time the physical form factor is updated, there is a chance to break traceability in the supply chain if incoming and outgoing product labels are not meticulously documented. This is exacerbated by a lack of standardized data formats and communication frameworks throughout the supply chain. All too often, there is a gap in a unit’s back mapping. Once this occurs, any chance to trace a problem to a source is jeopardized.
In the leading high-volume manufacturing (HVM) process flows, materials-enabled scaling has increased inline applications for compositional metrology.
A previous blog discussed how Fourier transform infrared (FTIR) spectroscopy was used for inline composition measurements. These measurements informed advanced process control for the wafer-level processing of selectively etched 3D NAND wordlines and DRAM capacitor profiles.
FTIR metrology has further HVM applications, including incoming substrate quality assurance, hardmask selectivity qualifications in the middle of the line, and verification of Low-K porogen evolution during interlayer dielectric (ILD) depositions on the back end of the line. These examples illustrate how FTIR modeling delivers metrics based on materials’ bond types for compositional process control.
It may surprise you, but when it comes to chips in electronic braking systems, airbag control units, and more, automotive manufacturers are still using 10-year-old technology — and with good reason.
For the automotive industry, the reliability, stability, and robustness of electronic components are critical, especially when it comes to meeting the stringent Automotive Electronics Council (AEC) Q100 standards that fabs need to follow. Some in the industry would not only rather keep using proven older chips over new ones, but they might even call for the construction of new fabs for older chips. In other words, tried and true is better than new and improved.
After TSMC announced plans to construct a new fab in Arizona, the Taiwan-based company disclosed that they are considering building new fabs in Japan and Germany. While the Arizona fab will focus on producing 5nm nodes using extreme ultraviolet lithography (EUV) technology, the new plant in Japan reportedly would focus on the 28nm node. This 28nm fab in Japan would be in addition to a 28nm fab expansion in China.
Given that the latter node was introduced in 2008 and is not regularly used today to build central processing units (CPU) and graphics processing units (GPU), the question arises, why is TSMC building not one, but three new fabs centered around 28nm node production? The answer is simple: customer demand.
And in this case, that demand is powered by devices and applications that use augmented reality (AR) and virtual reality (VR). Most of the devices, including those that use CMOS image sensors (CIS), are manufactured on 28nm to 80nm node technology. This is why major foundries, including TSMC and Samsung, are preparing to ramp up their volume production for these more mature nodes.
As a further illustration of the demand for the 28nm node, consider this: Apple is planning on manufacturing compact, high-resolution, micro organic light-emitting diode (OLED) display devices on silicon wafers, and Sony is planning on building image signal processing (ISP) devices; both companies will be using 28nm node technology.
AR overlays digital content and information onto images of the physical world captured by camera, and it is one of the biggest technology trends now. Apps like Snapchat and games like Pokémon GO first popularized AR, but the technology is predicted to become a part of our daily lives, influencing how we shop at brick-and-motor stores or drive (or not drive in the case of autonomous vehicles) our cars.
VR, meanwhile, is already widely used at work and home. While some gamers have embraced VR with a passion, advanced manufacturers regularly use VR to train employees. As for my company, Onto Innovation, we adopted and started using VR technology — in this case, Oculus from Facebook — for training and field support during the pandemic since some people could not meet face-to-face due to travel restrictions.
These incredible advancements in the use of AR and VR wouldn’t be possible without CIS. And with both AR and VR growing in popularity, there is no doubt that CIS applications will increase in the future.
The semiconductor industry is constantly marching toward thinner films and complex geometries with smaller dimensions, as well as newer materials. The number of chemical mechanical planarization (CMP) steps has increased and, with it, a greater need for within-wafer uniformity and wafer-to-wafer control of the thin film layers.
Process engineers have typically adopted over-polishing and re-working as part of the standard operating procedure to reach the desired end point and required film uniformity on the wafers. This is because the current generation of integrated metrology toolsets are based on relatively simple optical techniques, such as reflectometry, and do not have the inherent high resolution offered by off-line techniques, such as ellipsometry, which are technically complicated and cost prohibitive to implement as integrated solutions on process tools.
When it comes to thin film residuals, the current steps in the CMP process — with both over-polish and rework steps playing prominent roles — are inefficient and result in lower yields.
The next generation of CMP tools from leading suppliers are targeting a 100% increase over current throughput, going from 80 to 100 wafers per hour to more than 200 wafers per hour. In order to achieve the expected increase in throughput, the time currently being spent on offline feedback and rework is simply not feasible as a part of a process control strategy.
If the true potential of these next-gen CMP tools is to be reached, these CMP tools must be installed with integrated metrology capable of measuring extremely thin films and accurately reporting the end point, thereby eliminating the need for offline metrology. With this requirement, integrated metrology modules will need additional input and data processing capability to measure sub-50Å residual films in a CMP environment.
A recent internal study between Onto Innovation and Micron indicates that a hybrid metrology approach can be effective in improving the measurement accuracy of thinner films. This approach combines measurements from different steps in the process and then uses that information to enhance the data analysis of the integrated metrology tool via machine learning. Such an approach provides accurate film thickness discrimination and enables the proper end point in CMP. This reduces the need for over-polishing and significantly reduces the rework rate.
When it comes to multi-chip module (MCM) manufacturing, fan-out wafer-level and fan-out panel-level packaging have received a lot of coverage recently. Every week, it seems like there is an announcement about “Company XYZ” moving their products into the fan-out wafer-level packaging (FOWLP) or fan-out panel-level packaging (FOPLP) space. But these moves come with challenges that didn’t exist in the advanced packaging assembly space years ago. And it’s these challenges that today’s MCM manufacturers need to address.
Consider this: at the most ambitious panel manufacturing facilities, masking layers may now number a dozen or more layers. Couple that with the fact that there may be more than 60 days of cycle time at some FOWLP facilities, and it becomes clear that the issues MCM factories need to address are looking similar to the issues front-end (FE) fabs faced in the 1980s.
Back then, FE operations drove many of the requirements — from factory automation to data collection and analytics — that we take for granted in today’s semiconductor industry.
The reasons why defect and yield management systems were important to fabs in the 1980s are the same reasons defect and yield management systems are needed now at MCM factories. This holds true for die-first fan-out wafer-level manufacturing and die-last fan-out panel-level manufacturing.
When it comes to FOWLP manufacturing, the operational processes are similar to the operational processes used in semiconductor manufacturing, with lithography, film deposition and etching all playing roles. The two manufacturing environments have several common steps, film etching and polishing being the most obvious. Much like the FE, these MCM tools need dynamic controls and run-to-run management in order to properly function, day in and day out. These facilities can leverage the lessons that have been learned from decades of excursion events and ever faster yield ramps in FE fabs by including integrated metrology defect and yield systems during the initial MCM facility build out.