When the subject of hybrid bonding is brought up in the industry, the focus is often on how this technique is used to manufacture CMOS image sensors (CIS), an essential device for today’s digital cameras, particularly those found in smartphones. As such, CIS is a common touchpoint given the ubiquity of mobile phones, whether you hold a product from Apple, Samsung or Huawei in your hands.

But while today’s CIS devices currently dominate the use of hybrid bonding, high-performance computing (HPC) is emerging as a new high-growth application for hybrid bonding. This is a result of the trend toward finer pitched interconnects in advanced 3D packaged memory technologies. In addition, the market share of high-end performance packaging, including both 2.5D and 3D packaging, is expected to be $7.87B by 2027, with a compound annual growth rate (CAGR) of 19% from 2021 to 2027, according to Yole Développement. As for 3D stacked packaging alone, it is expected to grow at a CAGR of 58% to 70% during the same period.

Using direct Cu-to-Cu connections instead of bumps and suitable for pitches less than 10μm, hybrid bonding often involves the direct stacking of two wafers, with the space between the two planarized surfaces approaching zero. Hybrid bonding has advantages over conventional micro-bumping, such as enabling smaller dimension I/O terminals and reducing pitch interconnects. But while both hybrid bonding and conventional micro-bumping support higher-density interconnect schemes, hybrid bonding is an expensive process compared to bumping and requires much tighter process control, especially in the areas of defect inspection, planarity measurement and void detection.

While wafer-to-wafer bonding has already been demonstrated for NAND devices and is currently used in CIS manufacturing for the integration of the imager layer and logic, DRAM manufacturers are also looking to adapt hybrid bonding to replace bumps. Utilizing a hybrid bonding interconnect scheme capable of reducing the overall package thickness by tens and possibly hundreds of microns in certain situations, HBM (high-bandwidth memory) die are vertically stacked in 4,8,12,16 die stacks. The gap between each die is about 30μm when bumps are used, but the gap is nearly zero with hybrid bonding.

A recent study shows the radio frequency (RF) filter market growing steadily by nearly $16 billion from 2019 to 2024 at a compound annual growth rate (CAGR) of approximately 20%, according to Technavio. The strong growth in the RF filter market is driven by the increased adoption of 5G technology, the surge in smartphones using 5G, and commercial and consumer devices dependent on internet of things (IoT) applications. Together, these factors are some of the most significant players driving society’s digital transformation.

However, the RF filter market is faced with many of the same challenges the semiconductor industry as a whole is experiencing, including the need to pack more into increasingly smaller spaces. In each successive generation of RF filters, the number of filters has not only steadily increased, the rising number of filters has led to a need for more stringent process monitoring and control. A frequency accuracy, 3σ of 0.1%, requires film thickness control within the same accuracy or better.

Let’s look at one RF filter component, a bulk acoustic wave (BAW) resonator. A BAW is a piezoelectric structure sandwiched between the top and bottom electrodes. The resonant frequency depends on the acoustic velocity and the thickness of the piezoelectric film, and the thickness of the electrode. The thickness of the top electrode as a mass loading layer can be dialed in to generate a frequency shift, which is often used to form a filter passband.

Since the RF filter process is directly correlated to thickness, extremely uniform films (~0.1% or better) need to be deposited. With the additional requirements of 5G to support higher frequencies and increased bandwidth, RF filter device manufacturers employ several different process knobs to tune the devices. For example, we see an increasing trend toward thinner layers to support higher frequencies, the adoption of Sc-doped piezoelectric materials to improve piezoelectric coupling and the addition of temperature compensation SiO₂ layers to the stack to improve the temperature coefficient of the resonator.

As technology nodes shrink, end users are designing systems where each chip element is being targeted for a specific technology and manufacturing node. While designing chip functionality to address specific technology nodes optimizes a chip’s performance regarding that functionality, this performance comes at a cost: additional chips will need to be designed, developed, processed and assembled to make a complete system solution.

At back-end packaging houses in the past, a multi-chip module (MCM) placed various packaged chips on a printed circuit board. Today in the advanced packaging space, fabless companies are using an Ajinomoto build-up film (ABF) substrate as a method of combining various chips into a smaller form factor. As the push for increased density in smaller multi-chip module packages increases, process cost increases as well. Along with rising costs, the cycle times needed to process ABF substrates with ever more redistribution layers (RDL) also increases. Consequently, the need for back-end packaging houses to maintain process control and detect defects is going to be similar to what front-end fabs encountered in the 1990s.

Currently, substrates are 100µm to 150µm thick. As with front-end semiconductors, Moore’s law is going to come into play with advanced substrate packaging technology. Line width/interconnects are going to shrink, and the need to be able to control and detect feedback will grow.

Reticle exposure on a non-ridged substrate inherently will require better control for rotational, scaling, orthogonal and topology variation compensation. One solution is to use a feed-forward adaptive-shot technology to address process variations, die placement errors and dimensionally unstable materials. Such a solution uses a parallel die-placement measurement process, while advanced analytics provide a means to balance productivity against yield.

Displacement errors can be measured on a lithography tool, but the measurements are slow, typically taking as much time to conduct as the exposure. But moving the measurements to a separate automated inspection system and feeding those corrections to the lithography system can double throughput. In addition, yield software adds predictive yield analysis to the externally conducted measurement and correction procedures and increases the number of die included in the exposure field up to a user-specified yield threshold.

Ajinomoto build-up film (ABF) substrate has been a key component in chip manufacturing since its introduction shortly before the turn of the millennium. Substrates made with Ajinomoto build-up film – an electrical insulator designed for complex circuits – are found in PCs, routers, base stations, and servers.

Looking ahead, the ABF substrate market will continue to grow, with revenue up last year due to the strong demand for 5G, high-performance computing (HPC), servers and graphic processing units (GPU), as well as from the automotive industry. According to Goldman Sachs, the total demand for the ABF market should maintain a CAGR of 28% from 2022 to 2025. Like so many other essential components in the global supply chain, there is a shortage of ABF substrates.

But rising demand and supply chain issues aren’t the only factors contributing to the shortage of ABF substrates. Larger package sizes and an increasing number of layers for these high-technology products also play a part; after all, these larger packaging sizes result in fewer packages per ABF substrate. And since the manufacturing of ABF substrate is a build-up layer process, a defect in any one layer can hamper the final yield of the entire substrate. Given these factors facing the ABF substrate market, yield control becomes even more important than it was before.

The new year is always a wonderful time to take a deep breath, hold it and reflect on the past 12 months while planning for the year ahead. In the semiconductor industry, we have never seen a year like 2021, one with so many surprises combined with so much growth.

In 2021 we saw semiconductor manufacturing expansions accelerate across the value chain. Advanced logic was especially pronounced, with leaders seeing the opportunity to serve the growing market for high-performance compute or hyperscalers to power artificial intelligence (AI) engines in a wide range of applications. But 2021 will be remembered for broad demand growth, with 5G adoption in mobile handsets and base stations continuing to double each year. This drove a strong surge in the introduction rate of next-generation mobile handsets, which ushered in higher demand for camera chips, power, and memory.

In addition, the industry managed through national concerns about semiconductor technology challenges from the ongoing pandemic, and, as a result of the sharp increase in demand, a worldwide supply chain shortage of chips compounded by logistics challenges around the globe.

Against this backdrop, companies like Onto Innovation will see a growth of 40% year over year, and demand is continuing to rise in 2022. All the drivers are the same for the new year as in 2021, but we also see an increased focus on compound semiconductor devices, particularly for power devices supporting the global emphasis on transitioning from the 130-year-old combustion engine to electric vehicles (EVs) and the world’s critical need for smarter power grids that allow more renewable energy sources to come online. Along with that, we project higher levels of investment in heterogeneous packaging technology for 2022 to support the next generation of AI engines and high-performance integrated modules, such as those for 5G communication.