A new metrology system uses spectroscopic ellipsometry at mid-infrared wavelengths to provide accurate critical dimension and profile measurements of high-aspect-ratio (HAR) holes in 3D NAND memory. This information is essential for developing and controlling the fabrication process. The non-destructive technique exploits unique optical properties of mid-IR radiation to extract information that has not previously been available on a robust platform suitable for in-fab use. We look at two examples: channel holes, which have aspect ratios as high as 60:1 and eventually become vertical strings of memory cells in 3d NAND memory, and the holes in the hardmask, which have aspect ratios up to 25:1 and are used to etch the channel holes.

Ellipsometric optical critical dimension (OCD) metrology in the ultraviolet to near infrared (190 nm to 1.7 mm) spectral range is a well-established process control technique. It can measure buried features inaccessible to top-down non-destructive optical, electron, or ion imaging techniques, but it has limitations when applied to the extreme 3D and high aspect ratio features of 3D NAND devices. As more devices become inherently three-dimensional and scale vertically, the ability to measure the exact dimensions of buried features and re-entrant geometries will become increasingly important.

The transistor channel strings in the most advanced 3D NAND devices begin as high-aspect ratio holes (hereafter channel holes) etched through a stack of alternating silicon dioxide and silicon nitride (or polysilicon) layers with 128 or more layer-pairs. Etching holes with 100 nm diameters and depths greater than 6 mm (aspect ratios greater than 60:1) is challenging. The etch process uses a hard mask with holes of similar diameter and depths up 2.5 microns, giving them aspect ratios of 25:1 and presenting challenges similar to the channel hole etch. Figure 1 illustrates these structures schematically. An ideal etch process would yield a perfectly cylindrical hole with a uniform circular profile along its full length across the entire surface of a 300mm wafer. Realizable etch processes show significant deviations from cylindrical profiles both within a wafer and from wafer to wafer. Developing and controlling these processes requires the ability to measure hole profiles. Having this measurement capability inline accelerates process learning during the device development stage and is also critical even after the process has been transferred to high volume manufacturing where it proliferates to more etch chambers.

Analysts are projecting strong growth in advanced packaging, with CAGR through 2026 approaching 7% across the segment; much higher for certain high-end technologies, including 3D stacking, embedded die, and fan-out. Outsourced assembly and test (OSAT) firms, which package finished die manufactured by independent device manufacturers (IDM) and foundries, will be challenged by the complexity of the advanced packaging processes and will face stiff competition, in many cases from their own customers. If they are to thrive, or perhaps just survive, they will need to embrace smarter manufacturing approaches.

The historical division between front-end device manufacturing and back-end packaging/testing is the result of their vastly different cost structures and process complexity. The relative simplicity of the back-end process led OSATs to compete primarily on price, seeking always to minimize costs and maximize volume. Simple processes were simple to control. The acquisition, storage, and analysis of process data were costs to be avoided wherever possible. Advanced packaging processes have introduced a host of new variables that must be controlled to ensure process yield and product reliability.  Process data is no longer a cost to be avoided, but should be considered an essential asset to be leveraged to maximize profitability.

Meanwhile, as they accommodate increasingly complex processes, OSATs confront encroachment in their markets by sophisticated competitors who may also be their customers – IDMs and foundries who have outsourced a significant portion of their production to OSATs but have also maintained their own internal back-end capabilities. Advanced packaging processes have been described as the migration of front-end like processes to traditionally back-end applications. With this evolution, the advantage device manufacturers once had, by outsourcing assembly and test to avoid diluting their expertise with low-value processes, has greatly diminished. More importantly, these customers-turned-competitors are already comfortable with managing complex processes – they wrote the book. In addition to IDMs and foundries, substrate and printed circuit board (PCB) suppliers, electronic manufacturing services (EMS), original design manufacturers (ODM), and others see the opportunity presented by the significant growth forecasted for advanced packaging.

Data is the life blood of smarter manufacturing – acquiring it, storing it, organizing it, analyzing it, sharing it. Without leveraging it you are not just blind; in the competitive environment of semiconductor manufacturing, you will probably not survive. OSATs are not new to data collection and management. After all, testing is part of their name. But test data is product/function focused. In its simplest form it is go/no go. Functional testing may go beyond that, to measure how well it works, if for no other reason than to identify the best devices and sell them for premium prices. Smarter manufacturing requires data on a whole new scale – data that is both deep and broad.

In their continuing drive to pack more computing power and speed into less space, semiconductor manufacturers are using advanced packaging (AP) processes to integrate multiple die of different types within a single package and to increase input/output (I/O) connectivity for large, complex chips. The use of front-end-like processes to create ever smaller features on ever larger substrates is increasing the need for process control and inspection in AP processes. Novel materials like organic polymer dielectrics pose special challenges to conventional front-end optical technologies. Our new illumination technology, Clearfind®, specifically addresses these issues to provide high-sensitivity defect detection.

Packaging evolution

Packaging processes have evolved from relatively simple, inexpensive technologies to costly, complex processes that have adopted and adapted process technologies developed for wafer fabrication. Some of these processes are discussed in the sections below.

Wire bonding. Traditionally, packaging uses thin wires bonded between I/O pads at the edge of the chip and a wire frame that includes pins for connection to a printed circuit board. The chip and frame are encapsulated for protection from the external environment, resulting in a final package that is much larger than the chip.

Flip chip. Chip-scale processes, like flip chip, form contact pads on the top surface of the die, which, when the separated die are flipped over, mate with solder balls on a connecting package substrate. Flip-chip packages allow many more I/O connections because the entire surface of the chip, not just the edges, can be used for contacts. The resulting package is smaller than wire bonding, but usually larger than the chip.

Wafer-level processing. Wafer-level processing (WLP) uses front-end-like processes to form packaging structures on chips while they are still part of the wafer on which they are fabricated. WLP has the benefit of creating small packages – the same size as the chip – but that small size ultimately limits the space available for I/O connections.

Fan-out wafer-level processing. Fan-out wafer-level processing (FOWLP) offers increased I/O capability. Separated chips are embedded in a round substrate with space added between the chips. Overlying redistribution layers (RDL) route signals from contacts on the top surface of the chip to contacts on the top surface of the larger substrate extending beyond the area of the chip itself. The round, wafer-like form factor of the reconstituted FOWLP substrates permits the use of process equipment and handlers designed for wafer processing with minimal modification. But it also limits the size of the substrate (and therefore the number of die that it can contain), and it wastes space near the curved edges of the substrate where rectangular die/packages do not fit efficiently.

Fan-out panel-level processing. Fan-out panel-level processing (FOPLP) is similar to FOWLP except the panel substrates are not limited to wafer-like form factors. They can be rectangular, to increase spatial efficiency, and larger, to process more die per panel at lower cost per die.

Gate-all-around (GAA) transistors offer significant performance advantages at advanced nodes, but only at the cost of significant increases in process complexity. Complicated three-dimensional structures and shrinking critical dimensions make precise, accurate metrology in GAA manufacturing processes both more important and more challenging. Scatterometry-based optical critical dimension (OCD) metrology has become mainstream in the last several generations of semiconductor development, in part because of its ability to measure three dimensional shapes and subsurface/re-entrant features. The latest generation of OCD systems combines improvements in signal-to-noise ratios, signal fidelity and advanced machine learning capabilities that allow it to support the most challenging GAA process steps with repeatable measurements and production worthy throughput.

Silicon Semiconductor technical editor Mark Andrews recently spoke with Onto Innovation’s CEO Mike Plisinski about the merger of Nanometrics and Rudolph Technologies. Plisinski explores the benefits, challenges and opportunities of forming a new semiconductor supply chain entity by combining two industry leaders.

MA – When resources combine post-merger, each company contributes expertise, viewpoints and strategies which creates both challenges and opportunities. Looking at the merger from the perspective of each company, what are the primary near-term benefits and what might the industry expect from Onto Innovation over time?

MP – When I think about the benefits of the merger, I put them primarily in three categories: scale, scope, and synergy. Onto Innovation is now the fourth largest (by revenue) wafer fab equipment supplier in the U.S. and among the top 15 in the world. We have over $300 million in cash, cash equivalents or marketable securities and no debt. That gives us a lot of options to invest in our future. We are one of a few companies that is an end-to-end supplier, with products and applications ranging from unpatterned wafer quality, through advanced front-end metrology and macro defect inspection to advanced packaging lithography and inspection in the back-end, with enterprise software solutions spanning the entire value chain.