Efforts at curbing carbon dioxide emissions are stepping up, with more electric vehicles on our roads and the installation of renewable energy sources on the rise. Alongside these advances, the makers of these green technologies are increasing the electrical efficiency of their offerings, with silicon-based power devices being ditched in favour of superior alternatives based on the likes of SiC.
Supporting this move are the superior physical properties of these compounds. Compared with silicon, semiconductors such as SiC have wider-bandgaps, a higher electron saturation velocity, a higher critical electric field and a larger thermal conductivity. Drawing on all these strengths, power transistors offer higher operating frequencies, higher power ratings, elevated operating temperatures, better cooling capability and lower energy loss – just the traits that the market wants.
Last summer, the semiconductor industry reached a significant milestone: one of the world’s top-tier fabs had begun production of the first 3D NAND chip with more than 200 layers. The announcement was significant but not a shock. Several other fabs had been progressing toward breaking the 200-layer barrier, so reaching the milestone was not a matter of if but when.
As significant as this advance is, the high-volume manufacturing challenges of producing high-aspect ratio (HAR) 3D NAND chips are considerable. One challenge is the ability to measure the tungsten (W) recess to the bottom of a 3D NAND device following the replacement gate process. Presently, there is no in-line process control solution that can accomplish this. The reason for this is known: beyond just a few layers in the stack, the W recess becomes opaque in the ultraviolet/visible/ near-infrared region, the realm of many OCD systems, after just a few layers in the HAR stack. Additionally, increased wordline slit pitch scaling further reduces the already minimal optical signal from the top of the 3D NAND structure to the bottom.
Across the semiconductor industry, advanced integrated circuit (IC) substrate (AICS) supplies are low. The causes vary, from a limited number of suppliers who can meet performance requirements, to constrained production capacities, and increased demand resulting from the adoption of high-performance mobile devices, as well as advanced technologies like artificial intelligence (AI) and high-performance computing (HPC). And without question, the ongoing shortage of Ajinomoto buildup film (ABF), a necessary component of many AICS, plays a significant role as well. One area where this shortage of ABF and AICS is having a significant impact is in the manufacturing of flip-chip ball grid array (FC-BGA) packages—the most advanced substrates to meet the electrical and thermal requirements for IC chips with high numbers of I/Os.
To address the substrate shortage, suppliers of FC-BGA substrates are ramping up capacity. However, that acceleration comes with high costs due to the fact that the AICS process is burdened by low yields resulting from the presence of defects that are left undetected by many macro inspection systems. Furthermore, that inability to detect certain defects is potentially magnified as each new layer of ABF on the FC-BGA substrate is built up. In some cases, the number of layers of build-up may reach 20. With each additional layer, the potential for killer defects increases, whether the cause is ABF residue in laser-drilled vias, poor dry-film resist development, or the under and over-etching of Cu seed.
For decades, Moore’s Law has been a way to measure performance gains in the semiconductor industry, but the ability to double the density of transistors on a chip every twoyears is becoming increasingly challenging. With scaling reaching its limit, manufacturers are looking to advanced packaging innovations to extend the performance gains that the industry, and the world at large, have grown to depend on. Cu-to-Cu hybrid bonding is one way the industry is looking to extend ever-increasing I/O density and faster connections, all while using less energy.
Abstract
Ultrafast pump-probe measurements are used to characterize various samples, such as biological cells, bulk, and thin-film structures. However, typical implementations of the pump-probe apparatus are either slow or complex and costly hindering wide deployment. Here we combine a single-cavity dual-comb laser with a simple experimental setup to obtain pump-probe measurements with ultra-high sensitivity, fast acquisition, and high timing precision over long optical delay scan ranges of 12.5 ns that would correspond to a mechanical delay of about 3.75 m. We employ digital signal balancing to obtain shot-noise-limited detection compatible with pump-probe microscopy deployment. Here we demonstrate ultrafast photoacoustics for thin-film sample characterization. We measured a tungsten layer thickness of (700 ± 4) Å with shot-noise-limited detection. Such single-cavity dual-comb lasers can be used for any pump-probe measurements and are especially well-suited for ultrafast photoacoustic studies such as involving ultrasonic echoes, Brillouin oscillations, surface acoustic waves and thermal dynamics.
Heterogeneous integration enables multiple chips from varying Silicon processes to deliver superior performance. In large panel packages, present day limits on exposure field size forces manufacturers to ‘stitch’ together multiple reticles, which slows throughput and increases costs. Onto Innovation’s new JetStep® X500 system dramatically increases the exposure field up to 250 x 250 mm, slashing the number of exposures needed and cutting costs in FOPLP applications.
HIGH-PERFORMANCE compute, 5G, smartphones, data centers, automotive, artificial intelligence (AI) and the Internet of Things (IoT) – all rely on heterogeneous integration to achieve next-level performance gains. By combining multiple silicon nodes and designs inside one package, ranging in size from 75mm x 75mm to 150mm x 150mm, heterogeneous integration is one factor bringing us closer toward an era in which technology is beneficially embed into nearly all aspects of our lives whether it’s in the smart factories where we work, the self-driving cars that navigate the cities in which we live, the mobile devices that connect us to each other and the wearable devices that help us live healthier lives.
Regardless of the speed to which we are approaching this promising new era, this transition comes with increasing challenges, ones that are constrained by increasingly stringent requirements. The next-generation of heterogeneous integration technologies, and the fan-out, panel-level packaging that often accompanies it, will demand even tighter overlay requirements to accommodate larger package sizes with fine-pitch chip interconnects on large-format, 510mm x 515mm flexible panels.