Optical critical dimension metrology (OCD), also known as optical scatterometry, has been an integral part of the semiconductor “critical dimension” process control ecosystem for over two decades. OCD has inherent advantages over competing measurement techniques (such as CD-SEM, AFM, and cross-sectional SEM) because it is noncontact, non-destructive, fast (sub-second acquisition time), and extremely precise. OCD is an indirect, model-based optical technique (typically spectroscopic) that allows for the extraction of critical geometric parameters, asymmetries, and optical properties of periodically patterned structures at sensitivities much less than the measurement wavelength of light (>100x smaller).
Such sensitivity to multiple geometric parameters and material properties is due to the use of polarization-sensitive measurement techniques, like spectroscopic ellipsometry, and a sophisticated electromagnetic (EM) solver to simulate the spectral response of a periodic structure. If you already have a spectroscopic ellipsometer, you have the best way to measure thin film thicknesses and optical properties and a potential OCD tool to characterize 3D nanostructures. The missing piece is the analytical modeling software, which is where Ai Diffract, from Onto Innovation, comes in.
The United States is seeking to breathe new life into its domestic semiconductor packaging sector with the National Advanced Packaging Manufacturing Program (NAPMP), an initiative to “establish and accelerate domestic capacity for advanced packaging substrates and substrate materials,” according to a Commerce Department announcement from earlier this year [1]. In part, this program is the result of two very distinct trends, both of which are high-priority pursuits for governments and manufacturers. On the one hand, many nations like the U.S. are looking to shore up their semiconductor manufacturing capabilities to better protect themselves from potential geopolitical complications. Still another consideration is today’s rapidly growing demand for high-end applications like artificial intelligence (AI) and high performance computing (HPC) that are driving the need for advanced packages with 2.5 and 3D architectures. Such structures are built upon advanced integrated circuit substrates (AICS). Furthermore, the coming era of glass core substrates in advanced packaging will offer another level of challenges. The future is coming, and few want to be left behind.
Onto Innovation’s Monita Pau and Prasad Bachiraju contribute to the March 2024 edition of Semiconductor Digest.
Onto Innovation’s Doug Brown is pleased to publish, “The Great Lithography Debate: Copper Clad Laminate or Glass Substrates?” in the January-February 2024 issue of the Chip Scale Review.
Faster data transfer, greater heat dissipation, less power consumption and increased functionality are all qualities that chipmakers and their customers want from their devices. Since the dawn of the semiconductor industry, the pursuit of increasingly advanced nodes has served as the industry’s North Star. But for today’s voyagers, rough seas are ahead: these nodes have decreased in size, input/output (I/O) bumps on the chip have grown smaller—and with the shrinking of these bumps, their ability to mate directly to printed circuit boards (PCB) diminishes. The way to avoid this is to use advanced IC substrate (AICS), i.e., an intermediary substrate that enables progress in panel-level packaging (PLP) and chiplets.
Chiplets are a type of advanced packaging in which multiple die—such as memory, analog and other devices— are assembled in a single, large package along with a central processing unit (CPU) or graphics processing unit (GPU). With AICS, all of these chiplets can be co-packaged together in packages that may be as large as 120mm x 120mm each, which is a considerable increase from the 10mm x 10mm-sized packages of fan-out panel – level packaging (FOPLP). These large packages allow multiple die with smaller interconnects to be assembled and then redirected to larger contact bumps compatible with a PCB. None of this means the industry has left the pursuit of next-generation advanced nodes behind, or smaller packages for that matter.
Although the semiconductor industry has turned to chiplets and other advances to meet various next level performance needs and spur new innovations, advanced nodes remain key areas of development and advancement. But this move toward extra-large AICS packages signals the need for large exposure field, fine-resolution panel-level lithography systems that can expose entire panels using fewer exposures. The journey to a new era of chiplets and PLP, however, is fraught with challenges that must be overcome, including total overlay shift, yield loss and copper-clad laminate (CCL) substrate distortion. In this article, we will focus on these three challenges to the rapidly growing AICS market and outline several solutions that we have determined will enable manufacturers to address them.
Efforts at curbing carbon dioxide emissions are stepping up, with more electric vehicles on our roads and the installation of renewable energy sources on the rise. Alongside these advances, the makers of these green technologies are increasing the electrical efficiency of their offerings, with silicon-based power devices being ditched in favour of superior alternatives based on the likes of SiC.
Supporting this move are the superior physical properties of these compounds. Compared with silicon, semiconductors such as SiC have wider-bandgaps, a higher electron saturation velocity, a higher critical electric field and a larger thermal conductivity. Drawing on all these strengths, power transistors offer higher operating frequencies, higher power ratings, elevated operating temperatures, better cooling capability and lower energy loss – just the traits that the market wants.