Onto Innovation’s Doug Brown is pleased to publish, “The Great Lithography Debate: Copper Clad Laminate or Glass Substrates?” in the January-February 2024 issue of the Chip Scale Review.
Faster data transfer, greater heat dissipation, less power consumption and increased functionality are all qualities that chipmakers and their customers want from their devices. Since the dawn of the semiconductor industry, the pursuit of increasingly advanced nodes has served as the industry’s North Star. But for today’s voyagers, rough seas are ahead: these nodes have decreased in size, input/output (I/O) bumps on the chip have grown smaller—and with the shrinking of these bumps, their ability to mate directly to printed circuit boards (PCB) diminishes. The way to avoid this is to use advanced IC substrate (AICS), i.e., an intermediary substrate that enables progress in panel-level packaging (PLP) and chiplets.
Chiplets are a type of advanced packaging in which multiple die—such as memory, analog and other devices— are assembled in a single, large package along with a central processing unit (CPU) or graphics processing unit (GPU). With AICS, all of these chiplets can be co-packaged together in packages that may be as large as 120mm x 120mm each, which is a considerable increase from the 10mm x 10mm-sized packages of fan-out panel – level packaging (FOPLP). These large packages allow multiple die with smaller interconnects to be assembled and then redirected to larger contact bumps compatible with a PCB. None of this means the industry has left the pursuit of next-generation advanced nodes behind, or smaller packages for that matter.
Although the semiconductor industry has turned to chiplets and other advances to meet various next level performance needs and spur new innovations, advanced nodes remain key areas of development and advancement. But this move toward extra-large AICS packages signals the need for large exposure field, fine-resolution panel-level lithography systems that can expose entire panels using fewer exposures. The journey to a new era of chiplets and PLP, however, is fraught with challenges that must be overcome, including total overlay shift, yield loss and copper-clad laminate (CCL) substrate distortion. In this article, we will focus on these three challenges to the rapidly growing AICS market and outline several solutions that we have determined will enable manufacturers to address them.
Efforts at curbing carbon dioxide emissions are stepping up, with more electric vehicles on our roads and the installation of renewable energy sources on the rise. Alongside these advances, the makers of these green technologies are increasing the electrical efficiency of their offerings, with silicon-based power devices being ditched in favour of superior alternatives based on the likes of SiC.
Supporting this move are the superior physical properties of these compounds. Compared with silicon, semiconductors such as SiC have wider-bandgaps, a higher electron saturation velocity, a higher critical electric field and a larger thermal conductivity. Drawing on all these strengths, power transistors offer higher operating frequencies, higher power ratings, elevated operating temperatures, better cooling capability and lower energy loss – just the traits that the market wants.
Last summer, the semiconductor industry reached a significant milestone: one of the world’s top-tier fabs had begun production of the first 3D NAND chip with more than 200 layers. The announcement was significant but not a shock. Several other fabs had been progressing toward breaking the 200-layer barrier, so reaching the milestone was not a matter of if but when.
As significant as this advance is, the high-volume manufacturing challenges of producing high-aspect ratio (HAR) 3D NAND chips are considerable. One challenge is the ability to measure the tungsten (W) recess to the bottom of a 3D NAND device following the replacement gate process. Presently, there is no in-line process control solution that can accomplish this. The reason for this is known: beyond just a few layers in the stack, the W recess becomes opaque in the ultraviolet/visible/ near-infrared region, the realm of many OCD systems, after just a few layers in the HAR stack. Additionally, increased wordline slit pitch scaling further reduces the already minimal optical signal from the top of the 3D NAND structure to the bottom.
Across the semiconductor industry, advanced integrated circuit (IC) substrate (AICS) supplies are low. The causes vary, from a limited number of suppliers who can meet performance requirements, to constrained production capacities, and increased demand resulting from the adoption of high-performance mobile devices, as well as advanced technologies like artificial intelligence (AI) and high-performance computing (HPC). And without question, the ongoing shortage of Ajinomoto buildup film (ABF), a necessary component of many AICS, plays a significant role as well. One area where this shortage of ABF and AICS is having a significant impact is in the manufacturing of flip-chip ball grid array (FC-BGA) packages—the most advanced substrates to meet the electrical and thermal requirements for IC chips with high numbers of I/Os.
To address the substrate shortage, suppliers of FC-BGA substrates are ramping up capacity. However, that acceleration comes with high costs due to the fact that the AICS process is burdened by low yields resulting from the presence of defects that are left undetected by many macro inspection systems. Furthermore, that inability to detect certain defects is potentially magnified as each new layer of ABF on the FC-BGA substrate is built up. In some cases, the number of layers of build-up may reach 20. With each additional layer, the potential for killer defects increases, whether the cause is ABF residue in laser-drilled vias, poor dry-film resist development, or the under and over-etching of Cu seed.
For decades, Moore’s Law has been a way to measure performance gains in the semiconductor industry, but the ability to double the density of transistors on a chip every twoyears is becoming increasingly challenging. With scaling reaching its limit, manufacturers are looking to advanced packaging innovations to extend the performance gains that the industry, and the world at large, have grown to depend on. Cu-to-Cu hybrid bonding is one way the industry is looking to extend ever-increasing I/O density and faster connections, all while using less energy.