The semiconductor industry is entering an era where packaging innovation is as important as transistor scaling.
Artificial intelligence, high-performance computing systems, advanced smartphones, automotive electronics, and next-generation networking platforms increasingly depend on advanced packaging technologies to deliver the bandwidth, power efficiency, and functionality these applications demand, often in increasingly smaller footprints.
While much of the advanced packaging process control discussion focuses on defect detection, some challenges take of the form of subtle electrical conditions that can impact downstream yield, device reliability, and manufacturing consistency. These electrical effects are often invisible to traditional inspection and metrology methods, yet they can negatively affect downstream process performance, device reliability, and overall yield.
Residual charge control has emerged as a particularly important requirement for advanced packaging.
As manufacturers adopt new package architectures, they are also introducing a growing number of hygroscopic films and materials which are often combined with insulating layers and substrates. These materials require tighter environmental control, and in drier environments, residual and static charge can become a significant process concern. Plasma-based processing, deposition, cleaning, surface preparation, and bonding steps can further generate localized charge buildup across wafers and panels.
Figure 1: Advanced packaging process flow example (hybrid bonding). Residual charge monitoring is required at several process steps
To better address this challenge, manufacturers are increasingly adopting electrical process control methodologies. Onto Innovation provides these capabilities through technologies such as FAaST®, a non-contact electrical metrology platform capable of detecting residual surface charge.
The challenge, however, does not simply involve determining whether a charge exists. Manufacturers must understand where charge is accumulating, how uniformly it is distributed, and whether process changes are introducing new sources of variability. Without this level of insight, engineers may struggle to identify the root causes of yield loss, optimize process recipes, or ensure consistent manufacturing performance across multiple tools and chambers. The FAaST platform’s electrical metrology capabilities provide this insight into advanced packaging environments (Figure 1).
How does FAaST work?
This technology maps surface voltage across wafers and panels, enabling manufacturers to detect residual charge buildup and electrical non-uniformities. Through the rapid identification of localized charging hotspots and transformation of electrical conditions into actionable process information, the FAaST platform helps customers understand how process decisions influence package quality and manufacturing consistency. The value extends throughout the manufacturing lifecycle.
During development, the technology helps engineers compare recipes, evaluate new materials, and accelerate learning cycles by identifying electrical differences. During optimization, manufacturers can compare chambers, assess process uniformity, and quickly identify the sources of variability. In high-volume manufacturing (HVM), the same measurements provide ongoing monitoring to ensure critical processes remain within established control limits.
This ability to support both technology development and production control is a key advantage of the FAaST platform.
Rather than relying on indirect indicators or time-consuming electrical test structures, manufacturers gain direct insight into surface-voltage behavior. The result is faster feedback, improved process visibility, and more effective control of yield-critical steps.
Another important advantage of the FAaST platform is scalability.
The platform supports both full-wafer and panel-level measurements. This allows manufacturers to apply a common methodology across evolving packaging flows (Figure 2). As the industry explores larger substrate formats, maintaining consistent electrical control across larger form factors becomes increasingly important. Onto Innovation has expanded the capabilities of the FAaST platform to support panel-level applications while maintaining the same non-contact measurement approach used throughout the installed base.
Figure 2: Left) Full wafer mapping highlights local non-uniformities. Right) High resolution panel level mapping identifies patterns and localized hotspots.
In addition, the FAaST platform provides flexible measurement capabilities that align with customer requirements. Manufacturers can perform rapid full-wafer characterization to monitor overall process health or use higher-resolution measurements to investigate localized regions of interest, such as active areas and capacitors (Figure 3). This combination of throughput and resolution allows engineers to balance efficiency with detailed analysis across development and production use cases.
Figure 3: Intra-die surface voltage measurement with µm-resolution. Die size is ~16x30mm, while the zoom area is 4x5mm size
As advanced packaging continues to enable next-generation electronics, manufacturers will require process control solutions beyond traditional inspection and dimensional metrology. They will need actionable insights into the electrical conditions that influence yield, reliability, and manufacturability.
With the FAaST platform, manufacturers can monitor and control residual surface charge, helping accelerate process development, improve consistency, and enable a faster path to high-volume manufacturing.
After all, the next frontier in process control isn’t just visual—it’s electrical.
Roberto Fumagalli is a Product Marketing Manager at Onto Innovation.
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AI packages combine multiple advanced logic and high bandwidth memory (HBM) devices into a single architecture supporting higher I/O density, increased bandwidth, and improved power efficiency. But as AI packages grow in complexity and volume, manufacturers are under pressure to ramp quickly while maintaining high yield. For those looking to scale production of these complex packages, the economics favor approaches that improve substrate utilization and deliver more output per cycle. To accomplish this, manufacturers increasingly are adopting fan-out panel-level packaging (FOPLP) to maintain cost efficiency at scale.
Traditional wafer-based processing typically achieves approximately 55% substrate utilization with limited output per wafer. Panel-based approaches, however, can reach approximately 74% to 81% utilization, according to internal Onto Innovation estimates, while significantly increasing the number of packages produced per substrate, reinforcing the economic advantage of FOPLP at scale while improving material utilization across the substrate (Figure 1).
Figure 1: Substrate utilization efficiency improves from 55% for a 300mm wafer (supporting 6 units per substrate) to 81% for a 310×310mm panel (12 units per substrate), and reaches 74% for a 510×515mm panel (30 units per substrate).
However, FOPLP places new demands on lithography in the form of non-linear distortion, die shift, and overlay variation across the panel. These issues directly constrain yield and limit the ability of manufacturers to operate efficiently and at scale. Further complicating matters, traditional correction approaches offer ill-fitting lithography solutions for AI packaging, with most manufacturing strategies hampered by a fundamental tradeoff between yield and throughput. These challenges directly impact manufacturing cost, capacity utilization, and time to production.
Addressing these problems by conventional means can require extensive iteration to identify acceptable operating conditions. This is unacceptable for accelerated ramps to high-volume manufacturing (HVM). As a result, lithography itself has become a limiting factor in achieving consistent yield, controlling cost, and accelerating ramp time. These pressures are not incremental, however; they are structural consequences of the transition from wafer-based to panel-based manufacturing at larger formats and higher levels of integration. These challenges must be addressed for successful HVM.
In this article, we will examine how non-linear distortion and lithography correction tradeoffs hamper yield and throughput in FOPLP manufacturing and why conventional approaches impede ramp time to HVM. We will also explore how yield prediction technology enables earlier process visibility, reduces iteration, accelerates ramp, and lowers the cost of yield loss in advanced AI packaging.
Let’s start by taking a look at conventional correction strategies.
Figure 2: Heat maps of error distribution in regular FOPLP substrates. Blue regions indicate negative errors, while red regions represent positive errors. The heat maps reveal nonlinear pattern errors across the substrate.
Conventional Correction Strategies
As we mentioned earlier, in FOPLP lithography pattern errors and die shift contribute to yield loss. These errors originate during reconstitution and redistribution layer (RDL) processing and do not follow uniform distributions (Figure 2). Instead, they exhibit region-specific, non-linear spatial variation across the panel, often transitioning between positive and negative error regions. Because the distortion is non-linear and spatially non-uniform, traditional linear correction approaches cannot maintain overlay accuracy across the entire substrate. This results in localized misalignment, which directly reduces yield and introduces panel-level variability that is difficult for manufacturers to control in HVM. To address this challenge, multiple correction strategies are required to compensate for spatial variations at the exposure tool level. Unfortunately, each one introduces yield and throughput tradeoffs (Figure 3).
Figure 3: Lithography correction strategies to address the nonlinear errors in FOPLP substrate: a) Global correction: A single correction is applied uniformly across the entire substrate; b) Zone correction: The substrate is divided into zones, and corrections are applied to each zone individually; c) Die-by-die correction: Each die on the substrate is aligned and corrected individually; d) Site-by-site correction: Corrections are applied to multiple dies within a larger exposure field at once.
- Global correction applies a single adjustment across the panel. While this strategy maintains high throughput, it fails to compensate for localized errors, resulting in poor yield.
- Zone-based correction improves performance by applying localized corrections, but its effectiveness is limited, with observed yields typically ranging from 40% to 90%.
- Die-by-die correction provides the highest overlay accuracy by aligning each die individually, but this strategy is time-intensive and, as a result, reduces throughput.
- Site-by-site correction offers a partial compromise that improves yield while maintaining more practical processing times. This strategy, however, requires careful tuning. As a result, manufacturers must operate within a constrained optimization space.
In practice, selecting between these strategies requires manufacturers to balance yield targets against throughput requirements while maintaining production schedules and tool availability. Once a minimum yield threshold is defined by engineers, multiple operating points can emerge; the preferred solution is typically one that achieves acceptable yield while maximizing throughput. This is the sweet spot (Figure 4). Identifying the sweet spot requires extensive production constraints, repeated trials, and data re-analysis, resulting in increased engineering cost, extended development timelines, and delayed production ramp.
Figure 4: Determining the sweet spot in a regular lithography process requires significant time and effort because adjustments often necessitate repeated trials and data re-analysis.
Even when engineers are able to optimize this tradeoff, existing correction strategies remain fundamentally constrained. Because these strategies rely on predefined models and localized adjustments, they cannot completely compensate for complex, panel-scale distortion patterns. As a result, residual overlay errors persist, limiting achievable yield and forcing continued process optimization.
Determining optimal lithography conditions requires repeated experiments across multiple variables, including exposure settings, field configurations, and alignment strategies. Each iteration involves exposure, measurement, and analysis, increasing engineering workload, material usage, and development cycle time while extending development timelines.
Improving yield often requires adopting more granular correction strategies which inherently reduce throughput. This creates structural inefficiency: higher accuracy comes at the expense of productivity, limiting overall manufacturing output and reducing effective tool utilization in HVM environments.
Conventional workflows also rely heavily on post-lithography inspection to evaluate yield. Because defects are detected after processing is complete, corrective actions are inherently reactive, preventing manufacturers from addressing yield issues before additional process value has been added to the substrate. This results in avoidable rework, scrap, additional cycle time, and higher labor cost when excursions are detected late.
A New Strategy
To overcome these limitations, manufacturers need a new strategy that reduces reliance on iterative experimentation and enables earlier visibility into yield performance. This brings us to yield prediction technology (Figure 5).
Figure 5: Graphic depicting a yield prediction technology working scenario. An offline metrology tool captures data from a substrate, creating a comprehensive mapping dataset. The algorithms analyze the mapping data to predict overlay yield. The results are presented through a variety of visual formats, including detailed tables and graphical charts, enabling intuitive analysis, and facilitating root cause identification.
This technology addresses FOPLP lithography limitations by introducing a predictive approach to process control. Instead of relying solely on post-process inspection, this method enables manufacturers to forecast yield outcomes before lithography is completed, a clear time saver.
By combining offline metrology data with predictive analytics and machine learning algorithms, manufacturers can evaluate process performance in advance and select optimal process conditions prior to exposure and identify optimal operating conditions without extensive physical experimentation. This reduces iteration cycles, accelerates ramp, and enables manufacturers to converge on stable process conditions with fewer physical trials, while minimizing exposure to yield-driven cost risk.
Enabled through a combination of metrology data and advanced analytics, this yield prediction strategy not only predicts yield risk in the FOPLP lithography process, it supports earlier, more informed decisions on process tuning and rework and provides actionable guidance for optimizing production parameters.
The workflow for this strategy begins with offline metrology measurements that capture the detailed spatial mapping of pattern errors and die shifts across the panel. This mapping dataset provides a high-resolution representation of process variation. Predictive algorithms then analyze the data in conjunction with key process parameters, including exposure field configuration, die layout, panel layout, and overlay thresholds. Based on these inputs, the system predicts overlay error distributions and calculates expected yield performance. Then the results are presented through visualization tools, including yield dashboards, heat maps, vector plots, and histograms. With these tools at their disposal, engineers are enabled to identify the root cause of yield loss and evaluate alternative process strategies without executing full production trials. In addition, the analysis can be used to highlight dominant contributors to yield loss through more granular views such as residual overlay vector maps and axis-specific overlay error heat maps. This strategy supports faster root-cause isolation and targeted corrective action.
To assess the effectiveness of this predictive approach, we evaluated this strategy in HVM. Initial prediction errors ranged from 1.2% to 2.7%, demonstrating strong correlation between modeled and actual performance (Figure 6). Further analysis identified inspection variability as a key contributor to residual errors, particularly in cases involving ambiguous defect patterns requiring manual interpretation (Figure 7). Furthermore, differences in operator judgment introduced inconsistencies in measured yield results.
Figure 6: Yield prediction demonstration: a) Yield prediction dashboard: Includes predicted yield number, vector map and histogram charts for various deviations; b) Predicted yield heat map: The green dots indicate good overlay, while red and blue dots indicate overlay is out of threshold; the yield number is 97.45%; c) Actual yield heat map: The blue dots indicate good overlay, while red dots indicate the overlay is out of threshold—the actual overlay number is 98.82%. A comparison between the predicted and actual values reveals a difference of 1.37%. The results highlight opportunities for further refinement.
By standardizing inspection criteria and implementing training, this variability was reduced and prediction accuracy improved to within 0.2% to 0.8%. These results confirm predictive modeling can achieve the precision required for both development and production decision making. Beyond validation, this capability provides practical value across both development and manufacturing environments.
Accelerating Development
In development environments, yield prediction technology enables simulation-based process optimization. Engineers can evaluate multiple parameter sets, analyze overlay error behavior, and identify yield-limiting mechanisms without conducting repeated physical experiments. By reducing the number of required experiments, this approach shortens development cycles, lowers material consumption, and accelerates process qualification. It also improves the ability to understand process sensitivities and enables more targeted optimization strategies.
Figure 7: Overlay pattern variations can impact final yield due to operator errors: a) Via at pad edge; b) Via slight over pad edge; c) Good overlay. The metrology tool struggled with ambiguous patterns (e.g., see panels a and b), leading to manual judgment and variability-induced discrepancies of yield number.
Practically, this approach offers manufacturers a simulation-first workflow: teams can identify optimal parameters through simulation and then validate the predicted operating conditions using qualification substrates. This reduces both the time and cost associated with trial-and-error lithography learning (Figure 8). While these benefits are most evident during development, the impact extends further into production.
In production, yield prediction enables the earlier detection of defects within the lithography process flow, including in the coating, exposure, development, and post-treatment steps. Because early process defects can propagate through subsequent steps, the late discovery of defects can drive rework or, in some cases, permanent yield loss after additional value has already been added.
Figure 9: Visual charts and analytical tools of yield prediction technology showing: a) Various parameters for in-depth analysis; b) X-axis overlay error heat map; c) Y-axis overlay error heat map. A comparison of these maps reveals that the Y-axis exhibits the most significant overlay errors, which directly contribute to yield loss. This insight enables users to pinpoint the root cause of the issue and take corrective actions effectively, thereby improving overall process performance.
Figure 8: Vector maps of residual overlay errors are generated using yield prediction based on various process conditions. The maps are organized by shot size: a) 1×1, b) 3×3, c) 4×4, and d) 6×6. By leveraging this data-driven approach, users can accelerate process refinement, reduce trial-and-error iterations, and achieve more efficient improvements during the R&D stage, ultimately enhancing production efficiency and yield outcomes.
By enabling earlier visibility and decision-making, predictive analysis allows manufacturers to intervene before issues escalate (Figure 9). This reduces rework, limits scrap, and prevents additional value from being added to defective substrates. Equally as important, predictive analysis reduces the manpower, time, and costs associated with late-stage troubleshooting in FOPLP lithography, enabling engineering teams to respond earlier in the process and freeing them to focus on process optimization rather than reactive issue resolution.
In this way, yield prediction can be implemented as a form of preemptive quality control in mass production lines, supporting early stage screening and more reliable containment of excursions before they impact large substrate volumes (Figure 10). More importantly, yield prediction shifts defect management upstream, allowing engineers to correct for potential yield loss rather than reacting to it after completion. Taken together, these capabilities address the core constraints of FOPLP lithography.
Figure 10: The workflow of yield prediction technology for real-time, in-line process monitoring. By leveraging predictive insights, users can proactively address issues before they escalate, ensuring higher yield outcomes while minimizing rework, downtime, and associated costs.
Conclusion
FOPLP lithography is fundamentally constrained by non-linear distortion, yield–throughput tradeoffs, and the rising costs of AI packages. These challenges are compounded by conventional process control approaches that rely on iterative experimentation and post-process inspection, both of which limit ramp speed and efficiency and delay the transition to HVM.
Yield prediction technology addresses these limitations by enabling early visibility into the production process and reduces engineering reliance on trial-and-error optimization. This approach provides a practical and scalable method for improving both yield and throughput in FOPLP lithography.
By shifting process control from a reactive to predictive strategy, manufacturers can reduce yield loss, accelerate ramp to HVM, and improve overall manufacturing performance, thereby enabling more stable, cost-efficient production at scale.
Biography
John Chang is a Senior Principal Product Marketing Manager at Onto Innovation.
Jian Lu Staff is a Software Engineer at Onto Innovation.
Timothy Chang is a Senior Director of Applications Engineering at Onto Innovation.
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From consumer products to industrial applications, augmented reality (AR)/mixed reality (MR) technology is one of the most innovative interactive technologies on the market today. By overlaying digital information onto the physical world, AR/MR technology improves how people see, understand, and interact with their environment in real time. The industrial applications alone are cause for celebration, whether this technology is being used for training, assembly, or troubleshooting.
Be that as it may, one of the most significant challenges facing AR/MR lies in manufacturing the photonic components that control how light is generated, diffracted, guided, and delivered to the human eye.
An AR display usually consists of a light engine and an optical combiner. The light engine serves as a display image source, while the combiner delivers the displayed images to the viewer’s eye and transmits environment light (Figure 1). Surface relief grating (SRG) waveguides play a role in these optical combiners by coupling display light into, expanding it within, and diffracting it out of a transparent substrate toward the eye of the intended viewer. This component must deliver precise diffraction behavior while remaining transparent, lightweight, and scalable for high-volume manufacturing (HVM).
Balancing optical performance and manufacturability, however, places significant demands on fabrication and process control. Faced with this obstacle, device makers require solutions capable of addressing any negative impacts to launch timelines, unit costs, and OEM qualification.
Figure 1. Diagram of SRG waveguide-based AR display.
In this article we will discuss ways SRG manufacturers can address these challenges with an integrated process control solution tailored for the HVM of SRG. The solution combines optical critical dimension (OCD) metrology for the critical parameters of SRG such as grating depth, slanted angle, and periods; picosecond ultrasonic technology for the metal film thickness measurement; image‑based overlay (IBO) for precise overlay control in HVM specialty devices; and an automated optical inspection for defects integrated throughout the entire manufacturing process.
With these tools combined in a closed‑loop process control strategy, manufacturers have a framework that enables the consistent manufacturing of full‑color SRG waveguides capable of meeting the stringent optical and mechanical requirements of next‑generation AR/MR devices.
Navigating the Ramp to HVM
By coupling light into and out of a transparent substrate through precisely engineered diffraction gratings, SRG waveguides can deliver wide field‑of‑view, high brightness, and compact form factors. Unfortunately, manufacturers of SRG waveguides must face a host of challenges arising from multi‑layer and often double‑sided fabrication, with sub‑100nm alignment tolerances across large‑area substrates, if they hope to transition to HVM. The impact of these challenges, however, only grows as the manufacturing process goes on, increasing yield variability and making it difficult for makers of SRG components to meet the requirements expected by tier-one AR/MR customers.
To begin with, let’s turn to grating geometry. Manufacturers must control for period, depth, and slanted angle to ensure diffraction efficiency and uniformity across the field. Additionally, makers of these components must maintain proper thickness uniformity to avoid phase errors and color shifts; as such, thin‑film processes like mask deposition and etching must maintain exceptional thickness uniformity. Third, manufacturers must also maintain overlay accuracy between lithography steps, and they must do so within a fraction of the design tolerance to preserve red, green, and blue (RGB) multi‑period grating registration and double‑sided alignment. Finally, defect control is essential in the manufacturing process. After all, particles, scratches, and etch anomalies can cause scattering, reduce optical efficiency, and degrade image quality. Not surprisingly, the manufacturing process features a number of consequential steps (Figure 2).
In many cases, the process begins with the deposition of a chromium (Cr) hard mask on a SiO₂ substrate, followed by spin coating a resist layer. For master fabrication, electron beam lithography or deep ultraviolet lithography is used to pattern the grating structure. The resist pattern is then transferred to the Cr layer using a dry etching process, after which the residual resist is removed, leaving the Cr layer to serve as an etching mask for reactive-ion beam etching (RIBE). During RIBE, ionized argon beams are directed toward the substrate at an oblique angle to form the slanted grating profile. Once the target etch depth is achieved, the Cr layer is removed by chemical wet etching.
For HVM, the fabricated master grating is replicated using nanoimprint lithography (NIL) production due to its low cost and high throughput. In this process, the master pattern is first transferred into a polymer film to form a soft working stamp, which is then used to imprint a high refractive index (RI) resist layer. After imprinting, the pattern in the high-RI resist retains the same orientation as the original NIL template.
Figure 2. Basic flow in the manufacturing process of the surface relief grating waveguide.
These manufacturing challenges—spanning nanoscale grating fidelity, thin-film uniformity, overlay accuracy, and defect control—are tightly coupled and cannot be addressed in isolation without compromising yield or optical performance. Achieving stable, HVM requires coordinated visibility into each step of the SRG process. As it stands, makers of waveguide components rely on isolated measurements that diagnose symptoms without revealing root causes. In contrast, an integrated, closed-loop approach connects thickness, CD, overlay, and defect data, allowing engineers to correct process drift before it impacts customer-visible performance. By applying integrated metal film metrology, OCD measurement, image-based overlay control, and advanced defect inspection to the process flow, manufacturers are able to establish control and consistent SRG waveguide manufacturing, improving yield during ramp and reducing qualification cycle times, an important win for manufacturers ramping up HVM.
Tackling Thickness Non-Uniformity
As part of this integrated process control framework, thickness uniformity is a critical variable to address. In SRG manufacturing, thickness and uniformity must be precisely measured and controlled as it directly impacts downstream etch behavior, grating geometry, and ultimately optical performance. Uncontrolled metal film thickness is a frequent root cause of profile distortion and yield loss in SRG waveguides. When combined with CD, overlay, and defect control, the ability to measure metal thickness enables full process visibility across SRG manufacturing.
After deposition, the hard mask must be thick enough to remain intact throughout the entire etching process without being prematurely etched through. However, excessive thickness can distort the etched sidewall profile. Moreover, non-uniform thickness across the wafer can lead to variations in etch depth and grating tilt angle. This degrades diffraction efficiency and wavefront quality.
Figure 3. Cr and Al spectra and measurement result mapping.
To measure thickness, makers of SRG components can use an inline metal film metrology tool with picosecond ultrasonic technology. This tool offers rapid and precise determination of Al/Cr thickness across different substrates, delivering within wafer uniformity characterization that facilitates the early identification of process deviations.
In our demonstrations, we used an inline metal film metrology tool to gather data. The metrology system can measure metal film thickness across the wafer and with repeatable, stable precision over time, making it suitable for tight process control in high-volume SRG waveguide manufacturing. In production demonstrations, the results showed high-precision metal film thickness measurements with strong wafer-level uniformity and repeatability across representative substrates and multilayer film stacks (Figure 3). In addition, the metal film metrology tool achieved outstanding dynamic and static stability, thereby ensuring compliance with the rigorous demands of advanced process control as shown in Table 1. This level of control offered by the inline metal film metrology tool directly reduces grating profile drift between lots, lowering rework rates and preventing late-stage optical fallout during customer acceptance testing.
| Film information | Wafer Uniformity | Repeatability（1σ） | |||
| Average | Stdev | 1 σ | Static | Dynamic | |
| Si/Al3000Å | 2676.7 | 53.4 | 2.00% | 0.03% | 0.01% |
| Glass/Resin5000Å/Al3000Å | 2706.8 | 52.2 | 1.93% | 0.10% | 0.04% |
| Si/Cr220Å | 215.1 | 3.6 | 1.66% | 0.04% | 0.00% |
| Glass/TiO2600Å/Cr220Å | 223.2 | 4.5 | 1.99% | 0.15% | 0.10% |
Table 1. Cr and Al wafer uniformity and repeatability.
Meeting Tight Design Tolerances with OCD Metrology
In the fabrication of SRG waveguides, optical performance is highly sensitive to nanometer scale variations in grating period, depth, sidewall angle, and fill factor. Manufacturers of these components must adhere to the extremely tight design tolerances required for target coupling efficiency, polarization control, and chromatic uniformity throughout the manufacturing process.
To accomplish this, manufacturers can deploy OCD metrology based on rigorous coupled wave analysis (RCWA) to continuously monitor grating depth, CD, and sidewall angle before optical deviations propagate downstream. In demonstrations, we used an OCD metrology system based on RCWA to decode light scattering signals and simultaneously extract grating parameters across the entire wafer. Two types of SRGs were targeted: blazed SRGs and binary SRGs. Binary SRGs use a two-level stepped profile for phase or polarization control, and blazed SRGs use a slanted or ramped profile to efficiently direct light into a preferred direction.
Using OCD metrology, measurements of key parameters showed excellent agreement with reference metrology in representative SRG structures, confirming the suitability of OCD metrology for process control in SRG manufacturing. This stability enables tighter process windows and allows manufacturers to run closer to design limits without sacrificing yield, a critical need in situations where OEM specifications leave little margin.
Figure 4 .(a) OCD mode of blazed SRGs, matching with reference and dynamic performance. (b) OCD mode of binary SRGs, matching with reference and dynamic performance.
Preserving Full-Color Performance Through Precise Overlay
For manufacturers, maintaining overlay accuracy between successive patterning steps is a critical determinant of optical performance. Even small misalignments can cause coupling efficiency loss, field-of-view distortion, polarization imbalance, and chromatic aberrations.
Although a single SRG is typically formed in one patterning step, waveguide processes often require multiple patterning steps or the integration of several functional gratings on the same substrate. Representative cases include separate in-coupling and out-coupling gratings, multiwavelength gratings for full color operation, where red, green, and blue gratings of different periods are overlaid in the same location via multiple lithography or multiple nanoimprint patterning steps performed on both sides of the substrate, and precise registration with other micro-optical structures. These scenarios have stringent requirements. As such, overlay control at the submicron level is needed to preserve designed optical characteristics. Meeting these stringent alignment requirements in SRG waveguide architectures necessitates precise, wafer-scale overlay metrology. IBO techniques provide component makers with the capability to directly measure and control cross-layer and double-sided alignment in transparent substrates.
Figure 5. Bar-in-bar (BIB) and overlay fingerprint.
For our demonstration we used IBO technology enabling cross-layer and double-sided alignment in transparent waveguide substrates by matching grating pattern features. Using a bar-in-bar (BIB) mark for full map overlay measurement, demonstration measurements showed that the system achieved a precision of 0.26nm (X) and 0.18nm (Y) at 3σ (Figure 5). The measured tool-induced shift (TIS) was -2.63nm (X) and -0.71nm (Y), with corresponding 3σ TIS values of 0.62nm and 0.81nm, respectively (Table 2). Based on the industry standard 3σ definition, the resulting total measurement uncertainty (TMU) was 0.83nm in the X direction and 0.92nm in the Y direction. These results demonstrate that the overlay platform delivers sub-nanometer overlay capability and provides sufficient margin for the alignment requirements of high precision, full-color SRG waveguide manufacturing. In addition, the system provides correction parameters that can be directly applied to the lithography tool to compensate for systematic overlay errors.
| RG X Avg (nm) | RG Y Avg (nm) | RG X 3S (nm) | RG Y 3S (nm) | TIS X Avg (nm) | TIS Y AVG (nm) | TIS 3σ X (nm) | TIS 3σ Y (nm) |
| -71.8 | 36.0 | 0.3 | 0.2 | -2.6 | -0.7 | 0.6 | 0.8 |
Table 2. Overlay measurement statistics.
Detecting Submicron Defects
Defect inspection is critical to the manufacturing of SRG waveguides. Due to the unique nanoscale periodic structures and the optical sensitivity of SRG waveguides, even minor defects can lead to reduced diffraction efficiency, increased stray light, image non-uniformity, and other issues. As a result, defect inspection should be integrated throughout the entire SRG manufacturing process. In the mass production of SRG waveguides using NIL, manufacturers are enabled to detect organic defects from the photo resist, cleaning chemical residues, and high index resin which would normally escape detection under conventional brightfield or darkfield illumination schemes. In HVM undetected submicron organic defects can propagate across replicated stamps, turning a localized issue into a systemic yield problem.
The automated defect inspection system we employed provides fast and reliable inspection for submicron defects and the option to accurately measure 2D and 3D metrology features. Equipped with multiple illumination technologies, the inspection system is capable of capturing organic defects at or below 1µm. Standard optical inspection struggles with features at this size, opening the door to defect contamination that would otherwise be invisible but detrimental.
The Continued Evolution of AR/MR Technology
With the advent of mass production and declining costs of SRG waveguides, the coming years are poised to mark a transformative phase for AR/MR technology. This article presents an approach for full process control for the HVM of SRG waveguides, encompassing metal film metrology, OCD measurements of grating parameters, overlay alignment verification, and defect inspection—spanning from incoming substrate qualification to the validation of the final product.
The process‑control challenges discussed in this article extend across a broad class of AR/MR optical architectures, diffractive and meta-optical devices, and other nano-patterned optics manufactured at scale. Beyond SRG waveguides, the same process-control capabilities extend across a wide range of optical and photonic manufacturing applications, including other AR/MR waveguide architectures such as volume holographic and multi-level diffractive waveguides, as well as diffractive optical elements and meta-optics that rely on sub-wavelength pattern fidelity and precise depth control. These applications overlap strongly with optical thin-film stacks and functional coatings, micro-display manufacturing, and advanced optical and silicon-photonics packaging, all of which demand tight control of CD, overlay, film uniformity, and defectivity to reach HVM.
For manufacturers evaluating their next waveguide ramp, the key question is no longer whether SRG waveguides can meet optical targets, but whether their process control strategy can meet OEM schedules, cost models, and yield expectations at the same time. With the right integration of tools on hand, they can.
Biography
Alex Hong is a Senior Field Application Engineer at Onto Innovation, specializing in metal film metrology for semiconductor manufacturing, with additional expertise in optical critical dimension (OCD) applications.
The author would like to thank the rest of the team who worked on this article, including Onto Innovation’s Huayuan Li, Charles Zhang, Yuhang Lin, and Johnny Mu, along with Xiongwei Wang and Chenglong Jia of Sunny Optical Oulai Micro-Nano Optics (Shanghai) Co., Ltd.
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From the cars we drive to the devices we hold and the medical systems that safeguard our health, bipolar-CMOS-DMOS (BCD) technology is at the heart of many modern electronics.
Today’s vehicles are packed with electronics like power engine management, anti-lock braking systems (ABS), airbag controllers, and electric vehicle (EV) charging infrastructure, each one demanding a seamless integration of analog, digital, and power functions. In the case of smartphones, audio amplifiers, and smart home devices, BCD devices help balance power efficiency with high performance. Meanwhile, medical imaging systems, such as ultrasound, and advanced power management solutions, rely on semiconductor technologies like BCD devices to handle diverse electrical requirements without compromising accuracy or safety.
Important as BCD devices may be, what exactly are they?
BCD devices are an advanced semiconductor process technology that integrates three distinct types of transistors—bipolar, CMOS, and DMOS—onto a single chip. The integration of these three transistors enables the simultaneous handling of analog, digital, and power functions within a compact and high-performance platform, with each transistor type contributing unique strengths:
- Bipolar transistors offer high current handling and precise analog control.
- CMOS transistors provide low power consumption and high integration density for digital logic.
- DMOS transistors are optimized for high-voltage and high-current power applications.
For BCD devices to meet performance expectations, proper process control measures are needed, especially in the case of silicon-chromium (SiCr) thin films.
SiCr films play a critical role in BCD technology, primarily as precision resistive elements within analog and power management circuits (Figure 1.). SiCr resistors offer high stability, low temperature coefficient resistance (TCR), and excellent linearity, making them ideal for applications requiring accurate voltage and current control. Given the stringent reliability standards for BCD technology as demanded by the automotive industry and others, SiCr deposition must exhibit high reproducibility and minimal defectivity to support high-yield manufacturing and robust device performance under thermal and electrical stress.
Figure 1. Schematic of the BCD process, with SiCr film identified.
Uniformity across the wafer and repeatability between lots are critical. After all, minor thickness or compositional variations can lead to resistance drift which impacts analog accuracy and long-term reliability. Tight process control during the deposition step—including chamber stability, target conditioning, and plasma uniformity—ensures consistent film morphology and stoichiometry.
During SiCr sputtering, the precise regulation of specialty gas flow, in particular reactive gases such as nitrogen or oxygen, is critical, as their partial pressures influence plasma chemistry and the kinetics of silicide formation on the substrate. This silicide layer governs nucleation and grain growth, which directly affects grain boundary spacing and, consequently, TCR. Variations in gas flow can alter the stoichiometry and microstructure of the SiCr film, leading to shifts in TCR behavior, including the onset of a pronounced negative coefficient if the process is not tightly controlled.
Given the importance of these demands, manufacturers need the right tools on hand to maintain proper process control and optimize the performances of their BCD devices. In this article we will discuss the application of picosecond ultrasonic technology in two parts: one as a robust thickness metrology solution for qualifying SiCr deposition process and the second for excursion monitoring in BCD devices.
About Picosecond Ultrasonic Technology
Picosecond ultrasonic technology (PULSE™ technology) is a non-contact, non-destructive pump-probe laser acoustic technique for the measurement of metal film thickness. It is a proven workhorse in semiconductor fabs around the world. A 0.1ps laser pulse (pump) is focused to a small (~ 8´10mm2) spot onto a wafer surface to create a sharp acoustic wave. The acoustic wave travels away from the surface through the film at the speed of sound. At the interface with another material, a portion of the acoustic wave is reflected and comes back to the surface while the rest is transmitted. The probe pulse detects this reflected acoustic wave as it reaches the wafer surface. One can detect the change of optical reflectivity that is caused by the strain of the acoustic wave or alternatively detect, using a position sensitive detector (PSD), the deflection of the reflected probe beam that is caused by the deformation of the surface due to the acoustic wave. Both modes, reflectivity (REF) and PSD, are used in characterizing metal films. Knowing the speed of sound in the material, and the arrival time of the echoes, thickness is readily extracted using the first principles technique.
Film Thickness
With background on picosecond ultrasonic technology out of the way, we will turn our attention to the application of this technology as a robust thickness metrology solution for qualifying SiCr deposition process in BCD devices. To demonstrate this, we measured the nominal thickness of SiCr thin films using picosecond ultrasonic technology.
Figure 2a shows the raw data from the SiCr thin film. The acoustic echoes identified in the figure are used to calculate the thickness of the film using the speed of sound and round-trip transit time through the film. Nominally, textbook values for the longitudinal speed of sound would be used. In the case of SiCr films, the longitudinal speed of sound will vary from the bulk material and depend on the deposition process (sputtering, evaporation, etc.) and specific film composition (stoichiometry, density, etc.).
As a one-time calibration, we used cross-section transmission electron microscopy (TEM) to obtain SiCr film thickness and calculated the speed of sound for this specific process to be 69.7Å/ps. The modeled fit to the measurement is shown in Figure 2b.
Figure 2a. Raw data of reflectivity change vs time shown. The cross-wafer variation is identified by the shift in acoustic echoes.
Figure 2b. Modeled fit to measured data shown. The green curve represents the measurement, and the black curve represents the fit.
In Figure 3a, raw data from the DOE skew is shown. The shift in echo position between the different wafers demonstrates the sensitivity of the technique for monitoring the process. Within wafer uniformity profiles from 13 points across the wafer show consistent trends (Figure 3b).
Given the critical function of SiCr films in BCD device architecture, it is imperative to maintain highly uniform deposition with stringent process control to meet electrical and reliability specifications. Yield optimization is directly correlated with film uniformity as variations can significantly degrade device performance and long-term stability. As part of chamber qualification, more extensive sampling across the wafer, including to the edge, was performed (Figure 4). Those profiles are also consistent across the thickness skew.
Figure 3a. Raw data from the DOE thickness skew. Delta represents the skew in thickness from the target. The shift in echo position demonstrates the sensitivity for process monitoring
Figure 3b. Consistent cross wafer uniformity profiles for the three wafers.
Repeatability is a key metric in SiCr thin film metrology for ensuring robust process control and consistent device performance. Poor repeatability can obscure true process shifts, leading to incorrect corrective actions and potential yield loss. Gage capable repeatability measurements ensure compliance with automotive industry standards and are critical for long-term reliability. The dynamic repeatability data indicates performance is better than 0.5Å (1σ) and is more than sufficient to meet the process monitoring needs.
Figure 4. Forty-nine point wafer uniformity profiles for the three wafers, including measurements to the edge of the wafer. The profiles were consistent across the entire wafer.
As demonstrated, picosecond ultrasonic technology provides a precise, non-destructive method for measuring film thickness, validated against TEM calibration. The technique also offers exceptional repeatability and sensitivity, enabling manufacturers to monitor wafer-to-wafer and within-wafer uniformity with confidence. This capability is critical for maintaining tight process windows, as even minor deviations in thickness can lead to resistance drift and compromise analog precision. By integrating this metrology into chamber qualification and process monitoring, fabs can ensure consistent SiCr deposition, optimize yield, and meet stringent reliability standards.
Film quality
In picosecond ultrasonic technology, acoustic echoes are used to calculateSiCr film thickness. However, simultaneously available probe reflectivity data can be leveraged to provide information that can be used for process optimization (i.e., gas flow) and flagging process excursions. As such, this technique can be used to monitor the surface reflectivity of SiCr films; this application serves as a qualitative indicator of the film morphology and surface roughness and can be used for process control.
Figure 5. Surface reflectivity comparison for films having same target thickness but different reflectivity. Average reflectivity variation (top) across wafer is much higher than the thickness variation (bottom). Orange represents the lower flow rate, and blue represents the higher flow rate.
During the sputtering of SiCr films, gas flow has a strong influence on TCR as it impacts the film’s microstructure and stoichiometry (density and composition). This, in turn, determines the film’s stability, stress, and electromigration resistance in BCD applications. Uneven gas distribution causes local variations in thickness and composition leading to resistor mismatches and unpredictable TCR.
The surface reflectivity of the target wafer at two different gas flow rates is shown in Figure 5. Reflectivity data was collected at the same time as the acoustic data and shows the variation in surface reflectivity. At gas flow rate (b), the surface was more reflective corresponding to a smooth, dense film, whereas at flow rate (a), the reduced reflectivity indicates increased surface roughness which can degrade resistor uniformity and TCR stability.
Also, the thickness variation SiCr film is thinner at the higher N2 flow. N2 is known to affect silicide/nitride formation, grain spacing, etc., and impact both thickness and reflectivity. Studies are underway to characterize the impact of annealing temperature. The results are promising.
In summary, the surface quality of SiCr films plays an equally critical role in device stability and long-term performance. The study highlights how reflectivity measurements, captured alongside thickness data using the same picosecond ultrasonic platform, serve as a powerful indicator of film morphology and density. Variations in gas flow during sputtering were shown to significantly influence both reflectivity and thickness, underscoring the importance of precise control over deposition parameters. A smoother, more reflective surface correlates with improved resistor uniformity and predictable TCR behavior, while rougher films can degrade electrical performance.
Based on these results, we have demonstrated that reflectivity measurements, along with thickness measurements, can be leveraged for in-line monitoring to detect deviations in deposition parameters. By leveraging dual metrics—thickness and reflectivity—manufacturers gain a comprehensive, in-line process control solution that enables early detection of excursions and proactive corrections, ensuring robust SiCr thin film integration in advanced BCD architectures.
Conclusion
From automotive safety systems to medical imaging and consumer electronics, BCD technology enables the seamless integration of analog, digital, and power functions that modern applications demand. Yet, this versatility hinges on precise control of SiCr thin films whose stability and uniformity directly influence device reliability
Achieving this level of integration comes with significant manufacturing challenges, particularly in controlling SiCr film thickness and gas flow during sputtering, factors which directly impact resistor stability and temperature performance, which are critical for reliability in demanding environments. To overcome these hurdles, we propose using picosecond ultrasonic technology.
With picosecond ultrasonic technology, manufacturers have a powerful, non-destructive tool for monitoring thickness and reflectivity at the ready, one that ensures that SiCr films meets stringent performance standards. In doing so, manufacturers will be able to safeguard the integrity of BCD devices while supporting the continued evolution of new technologies across the automotive, medical, and consumer electronics sectors.
By Huayuan Li, Alex Hong, Johnny Mu, Timothy Kryman, and Priya Mukundhan
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Abstract
Picosecond Ultrasonics (PULSE™) Technology has emerged as a leading metrology solution for characterizing single-layer and multilayer metal films in advanced semiconductor manufacturing [1]. As a non-contact, non-destructive technique, PULSE Technology has become the tool-of-record across multiple device segments, including logic, radio frequency (RF), memory, microelectromechanical systems (MEMS), and flash memory. Its ability to measure both film thickness and elastic modulus [2,3] in-line makes it indispensable for process control and material characterization.
Backside metallization (BSM) is essential in semiconductor fabrication, particularly for power electronics, logic ICs, and advanced memory devices. It involves depositing metal layers on the wafer’s reverse side to improve electrical conductivity, thermal dissipation, and mechanical stability. As device architecture becomes more complex, precise control and measurement of BSM layers are critical for ensuring performance and reliability. Driven by demand from semiconductors, photovoltaic, MEMS, and LED sectors, the BSM market is expanding rapidly [4]. Technologies such as PVD, CVD, electroplating, and sputtering enable tailored metal stacks, but they also pose metrology challenges—especially for non-destructive, multilayer characterization. These metal layers typically range from 50 nm to 3 µm in thickness, with total stack thicknesses reaching up to 5 µm.
Accurate characterization of BSM layers is essential for ensuring device reliability, performance, and manufacturing yield. Traditional metrology techniques such as scanning electron microscopy (SEM), atomic force microscopy (AFM), four-point probe, X-ray reflectometry (XRR), and X-ray fluorescence (XRF) often face limitations in throughput, destructiveness, thickness limitations, or sensitivity to surface roughness. In contrast, Picosecond Ultrasonics offers a compelling alternative, providing high-precision measurements across a wide thickness range with micron-scale spatial resolution. Its ability to simultaneously resolve multiple layers in a single measurement, even on rough or non-planar surfaces, makes it particularly well-suited for BSM applications.
In this paper, we demonstrate the application of Picosecond Ultrasonics to backside metallization metrology. We present data showing its capability to measure both single-layer and multilayer metal stacks with excellent repeatability, long-term stability, and high throughput. The technology’s small spot size—on the order of microns—enables measurements on small pads as small as 15 µm, improving spatial resolution and enabling in-line monitoring on product wafers. Furthermore, advanced features such as dual modulation, crossed polarization, and adaptive measurement controls enhance performance on challenging surfaces, including aluminum and complex BSM stacks.
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Mid-infrared ellipsometry offers a powerful approach for non-destructive optical critical dimension (OCD) metrology in advanced semiconductor manufacturing. This technique supports in-line measurements of high aspect ratio structures, such as those found in 3D NAND memory devices. The incorporation of quantum cascade lasers and fast phase modulation allows rapid acquisition of Mueller matrix elements with high spatial resolution and sub- Å precision. Material-specific absorption in the mid-infrared range allows depth-resolved profiling of device structures, overcoming the limitations of conventional OCD. Rigorous coupled wave analysis is used to extract structural parameters from the measured spectra. Agreement with destructive reference metrology has been demonstrated on a variety of structures. The ability to measure multiple Mueller elements further enhances characterization of complex geometries, making mid-infrared ellipsometry a valuable tool for process control in semiconductor fabrication.
This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. This article appeared in Journal of Applied Physics (Vol.139, Issue 7) and may be found at https://doi.org/10.1063/5.0310009
DOI: 10.1063/5.0310009
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