As technology nodes shrink, end users are designing systems where each chip element is being targeted for a specific technology and manufacturing node. While designing chip functionality to address specific technology nodes optimizes a chip’s performance regarding that functionality, this performance comes at a cost: additional chips will need to be designed, developed, processed and assembled to make a complete system solution.
At back-end packaging houses in the past, a multi-chip module (MCM) placed various packaged chips on a printed circuit board. Today in the advanced packaging space, fabless companies are using an Ajinomoto build-up film (ABF) substrate as a method of combining various chips into a smaller form factor. As the push for increased density in smaller multi-chip module packages increases, process cost increases as well. Along with rising costs, the cycle times needed to process ABF substrates with ever more redistribution layers (RDL) also increases. Consequently, the need for back-end packaging houses to maintain process control and detect defects is going to be similar to what front-end fabs encountered in the 1990s.
Currently, substrates are 100µm to 150µm thick. As with front-end semiconductors, Moore’s law is going to come into play with advanced substrate packaging technology. Line width/interconnects are going to shrink, and the need to be able to control and detect feedback will grow.
Reticle exposure on a non-ridged substrate inherently will require better control for rotational, scaling, orthogonal and topology variation compensation. One solution is to use a feed-forward adaptive-shot technology to address process variations, die placement errors and dimensionally unstable materials. Such a solution uses a parallel die-placement measurement process, while advanced analytics provide a means to balance productivity against yield.
Displacement errors can be measured on a lithography tool, but the measurements are slow, typically taking as much time to conduct as the exposure. But moving the measurements to a separate automated inspection system and feeding those corrections to the lithography system can double throughput. In addition, yield software adds predictive yield analysis to the externally conducted measurement and correction procedures and increases the number of die included in the exposure field up to a user-specified yield threshold.
The ability to trace the genealogy of all the components in an electronic device has been getting more complex for decades. For many industries — automotive, defense, medical and others — the need to locate the source of a problem in near real-time is paramount to gauging the extent of that problem. The extreme case is when the issue occurs with a product that already has been distributed and used in the field. Complicating matters is the fact that the current chip shortage is pushing chip designers to second- and third-tier suppliers for their inventory.
Tracking information is not easily done given the number of times material can change hands during the manufacturing life cycle. Designs can incorporate IP modules from Parties No. 1, No. 2, and No. 3 (figure 1). These designs are blended into a singular chip by the device’s Design House. This chip is then built at Front-end Foundries No. 1 or No. 2. The completed chip can be tested and partially assembled at OSAT A, B, or C. Finished assembly into a multi-chip module (MCM) or printed circuit board (PCB) can take place at Assembly House No. 1 or No. 2 (or happen at Customer A if they provide the IP for a design for a device that can be assembled by Finished Goods Maker No. 1) before it is finally sold by the Design House to the End User or Final Goods Manufacturer A, B, C, D and more for insertion in their end product, after which it is again tested before being sold to the end customer.
This is a very simplified example of how complex a supply chain can be, but it is illustrative nonetheless.
Virtual v. physical traceability
At some point in the supply chain, units receive a physical marker that enables traceability as it progresses through the remaining chain of manufacturing agents. Prior to the application of a marker, reliance on a part’s origin is a function of accounting and accurate recordkeeping. Although this seems simple enough, it is complicated by the transition of “ownership” of the chip as it moves through the supply chain.
Tracing a chip’s origin includes its transformation through multiple physical form factors. These material changes frequently include moving from a lot/wafer/die physical structure to a singulated die on a piece of tape or reel to an assembled die in a package, or in a tray, or as an inserted chip in a multi-chip module or PCB — ultimately ending with the PCB being inserted into a larger form factor, such as an automobile or a computer server. Each time the physical form factor is updated, there is a chance to break traceability in the supply chain if incoming and outgoing product labels are not meticulously documented. This is exacerbated by a lack of standardized data formats and communication frameworks throughout the supply chain. All too often, there is a gap in a unit’s back mapping. Once this occurs, any chance to trace a problem to a source is jeopardized.
It may surprise you, but when it comes to chips in electronic braking systems, airbag control units, and more, automotive manufacturers are still using 10-year-old technology — and with good reason.
For the automotive industry, the reliability, stability, and robustness of electronic components are critical, especially when it comes to meeting the stringent Automotive Electronics Council (AEC) Q100 standards that fabs need to follow. Some in the industry would not only rather keep using proven older chips over new ones, but they might even call for the construction of new fabs for older chips. In other words, tried and true is better than new and improved.
When it comes to multi-chip module (MCM) manufacturing, fan-out wafer-level and fan-out panel-level packaging have received a lot of coverage recently. Every week, it seems like there is an announcement about “Company XYZ” moving their products into the fan-out wafer-level packaging (FOWLP) or fan-out panel-level packaging (FOPLP) space. But these moves come with challenges that didn’t exist in the advanced packaging assembly space years ago. And it’s these challenges that today’s MCM manufacturers need to address.
Consider this: at the most ambitious panel manufacturing facilities, masking layers may now number a dozen or more layers. Couple that with the fact that there may be more than 60 days of cycle time at some FOWLP facilities, and it becomes clear that the issues MCM factories need to address are looking similar to the issues front-end (FE) fabs faced in the 1980s.
Back then, FE operations drove many of the requirements — from factory automation to data collection and analytics — that we take for granted in today’s semiconductor industry.
The reasons why defect and yield management systems were important to fabs in the 1980s are the same reasons defect and yield management systems are needed now at MCM factories. This holds true for die-first fan-out wafer-level manufacturing and die-last fan-out panel-level manufacturing.
When it comes to FOWLP manufacturing, the operational processes are similar to the operational processes used in semiconductor manufacturing, with lithography, film deposition and etching all playing roles. The two manufacturing environments have several common steps, film etching and polishing being the most obvious. Much like the FE, these MCM tools need dynamic controls and run-to-run management in order to properly function, day in and day out. These facilities can leverage the lessons that have been learned from decades of excursion events and ever faster yield ramps in FE fabs by including integrated metrology defect and yield systems during the initial MCM facility build out.
The following paper presents a case study describing how to improve yield and fab productivity by implementing a frequent pattern database that utilizes Artificial Intelligence based Spatial Pattern Recognition (SPR) and wafer process history. This is important because associating spatial yield issues with process and tools is often performed as a reactive analysis, resulting in increased wafer scrap or die loss that could be prevented. The implementation of fab fingerprint technology proactively generates a pareto of high impacting process steps and tools based on a pattern score, enabling the production team to concentrate more efficiently on yield limiting events.
We depend, or hope to depend, on machines, especially computers, to do many things, from organizing our photos to parking our cars. Machines are becoming less and less “mechanical” and more and more “intelligent.” Machine learning has become a familiar phrase to many people in advanced manufacturing. The next natural question people may ask is: How do machines learn?
Recognizing diverse objects is a clear indicator of intelligence. Specific to semiconductors, recognizing various types of defects and categorizing them is an important task that initially was carried out solely by humans. Gradually, this classification process was automated by using computer programs running ever-evolving algorithms. Today, most defects are detected and classified by such systems in advanced facilities.
Before machine learning was widely used, there was a period when system set-up was done purely by humans. After learning about situations for a task through observation and experiments, engineers made rules and implemented them as programs for computers to run. In this implementation scenario, the machine does not learn, it just keeps repeating the process programmed, making decisions based on the embedded rules. This is a very labor-intensive approach—to extract the rules from human classifiers, create the programmatic logic to implement these rules, and to verify the result. Sometimes it’s very difficult, or impossible, to translate a decision-making process that humans do, often subconsciously, into computer language.