In the semiconductor industry, digital twins are the focus of a lot of attention, with substantial investments from industry players and governments alike. This year the European Union and the United States have pledged hundreds of millions of dollars in grants and funding opportunities, including the new CHIPS Digital Twin Manufacturing USA Institute. Ultimately, many people see great value in innovating, commercializing and scaling digital twin technology.
As with many trends, digital twins are the subject of speculation and fervor. Unfortunately, this enthusiasm can drive well intentioned users and organizations to choose solutions they don’t need – or spend too much time and money before arriving at reliable ones.
Panel-level advanced packaging technologies have been in development for more than a decade. They began as a way to reduce costs and improve yields for fan-out wafer level applications. Smartphone applications – particularly fingerprint sensors – promised the volumes that would make the investment successful.
However, memories of the fiasco of 450mm wafer efforts lived in the minds of many. Why make the investment in an ecosystem that may not demand high enough volumes to insure return on investment? Still, there were those who believed in the promise of panel-level packaging. Development efforts persevered, and PLP has moved through R&D and into pilot production. Still, through it all, many remained skeptical about there being high enough volumes to support it.
The Era of AI, coupled with the emergence of glass substrates, is set to change all that.
On September 30, 2024, I visited Onto Innovation’s headquarters in Wilmington, MA to attend the grand opening of its Packaging Applications Center of Excellence (PACE). The company has partnered with like-minded suppliers of the PLP ecosystem to accelerate the development of PLP technologies for both organic and glass substrates. These include 3D InCites Members: LPKF Laser & Electronics, Evatec, MKS-Atotech and Lam Research; as well as Resonac, Corning, and others.
Semiconductor manufacturing creates a wealth of data – from materials, products, factory subsystems and equipment. But how do we best utilize that information to optimize processes and reach the goal of zero defect manufacturing?
This is a topic we first explored in our previous blog, “Achieving Zero Defect Manufacturing Part 1: Detect & Classify.” In it, we examined real-time defect classification at the defect, die and wafer level. In this blog, the second in our three-part series, we will discuss how to use root cause analysis to determine the source of defects. For starters, we will address the software tools needed to properly conduct root cause analysis for a faster understanding of visual, non-visual and latent defect sources.
When it comes to data accessibility, the terms “secure” and “share” seem like two diametrically opposed words. Conventional wisdom would suggest that any effort to secure data would involve limiting access to that data, while sharing data would involve opening up access to that data for others to view and use.
As it turns out, semiconductor operations need to do both.
On the one hand, semiconductor companies often need to share data so others can leverage data for problem solving and improve their overall manufacturing processes. On the other, these companies need to know their data is secure and free from data leaks resulting in lost IP or negating a competitive advantage. The solution: secured data sharing.
Automated optical inspection (AOI) is a cornerstone in semiconductor manufacturing, assembly and testing facilities, and as such, it plays a crucial role in yield management and process control. Traditionally, AOI generates millions of defect images, all of which are manually reviewed by operators. This process is not only time-consuming but error prone due to human involvement and fatigue, which can negatively impact the quality and reliability of the review.
In the Industry 4.0 era, the integration of a deep learning-based automatic defect classification (ADC) software solution marks a significant advancement in manufacturing automation. For one, ADC solutions reduce manual workload – meaning less chance of human error and higher accuracy – and, two, they are poised to lower the costs associated with high-volume manufacturing (HVM).
Deep learning, a branch of machine learning based on artificial neural networks, is at the core of these ADC solutions. It mimics the human brain’s ability to learn and make decisions; this enables the system to recognize complex patterns in data without explicit programming. Compared to traditional methods, this approach offers a significant leap in processing efficiency and accuracy.
Abstract
In traditional semiconductor packaging, manual defect review after automated optical inspection (AOI) is an arduous task for operators and engineers, involving review of both good and bad die. It is hard to avoid human errors when reviewing millions of defect images every day, and as a result, underkill or overkill of die can occur. Automatic defect classification (ADC) can reduce the number of defect images that need to be reviewed by operators. The ADC process can also be integrated with AOI engines to reduce nuisance defect images to reduce AOI image capturing time. This paper will focus on how to utilize Onto Innovation’s TrueADC software product to build ADC classifiers using a multi-engine (ME) solution. The software supports CNN, DNN and KNN algorithms. The use of CNN and DNN are currently mainstream in the development of deep learning (DL) for ADC classification in the semiconductor industry. We will address how to improve classification by using multiple models in the classification process with unique algorithms. As a result, the user can achieve industry requirements with very demanding specifications, like high accuracy, high purity, and high classification rate with very low escape rates.