Efforts at curbing carbon dioxide emissions are stepping up, with more electric vehicles on our roads and the installation of renewable energy sources on the rise. Alongside these advances, the makers of these green technologies are increasing the electrical efficiency of their offerings, with silicon-based power devices being ditched in favour of superior alternatives based on the likes of SiC.
Supporting this move are the superior physical properties of these compounds. Compared with silicon, semiconductors such as SiC have wider-bandgaps, a higher electron saturation velocity, a higher critical electric field and a larger thermal conductivity. Drawing on all these strengths, power transistors offer higher operating frequencies, higher power ratings, elevated operating temperatures, better cooling capability and lower energy loss – just the traits that the market wants.
In recent years, power semiconductor applications have expanded from industrial and consumer electronics to renewable energy and electric vehicles. Looking to the future, the most promising power semiconductor devices will be insulated gate bipolar transistor (IGBT) and power metal oxide semiconductor field effect transistor (power MOSFET) modules.
During the manufacturing of these devices, metal films are deposited on the die of MOSFET and IGBT power devices. These layers of film have two main functions: they connect the elementary cells constituting the power dies to the source (power MOSFET) or emitter (IGBT) and allow for the welding of bond wires on the chip or for the solder bonding, facilitating thermal conduction. Because power devices run high currents at high-operating temperatures, the metal layers need to be properly controlled for electrical properties and thickness to enhance thermal conductivity.
Furthermore, power devices are transitioning from 6-inch to 8-inch wafers; this is happening at the same time as process windows are shrinking. As a result, measuring multi-layer metal thickness accurately and characterizing the uniformity of metal film deposition at the wafer edge has become increasingly important. For example, the front side of wafers requires deposition of a thick metal layer, typically 5µm or more of aluminum alloy. The uniform coverage of aluminum to conduct high currents across the entire wafer is key to device yield and reliability.
You’ve read the reports: the memory market is floundering as the semiconductor industry moves through another scarcity/surplus cycle.
Be that as it may, innovation is happening as the industry continues to pursue increasingly higher three-dimensional stacks, with 3D NAND stacks taller than 200 layers entering production.
However, there are challenges. Among those: conventional optical critical dimension (OCD) metrology systems have difficultly measuring the tungsten (W) recess in the wordline (WL) slit following the replacement gate step. This is particularly a problem as high-aspect ratio (HAR) stacks reach 96 layers or higher. For manufacturers, the ability to measure the W recess is critical. Under-etching the W replacement gates in the recess can cause wordlines to short, while over-etching the W gates can damage cells or cause a short from the wordline to the source line.
Last summer, the semiconductor industry reached a significant milestone: one of the world’s top-tier fabs had begun production of the first 3D NAND chip with more than 200 layers. The announcement was significant but not a shock. Several other fabs had been progressing toward breaking the 200-layer barrier, so reaching the milestone was not a matter of if but when.
As significant as this advance is, the high-volume manufacturing challenges of producing high-aspect ratio (HAR) 3D NAND chips are considerable. One challenge is the ability to measure the tungsten (W) recess to the bottom of a 3D NAND device following the replacement gate process. Presently, there is no in-line process control solution that can accomplish this. The reason for this is known: beyond just a few layers in the stack, the W recess becomes opaque in the ultraviolet/visible/ near-infrared region, the realm of many OCD systems, after just a few layers in the HAR stack. Additionally, increased wordline slit pitch scaling further reduces the already minimal optical signal from the top of the 3D NAND structure to the bottom.
For decades, Moore’s Law has been a way to measure performance gains in the semiconductor industry, but the ability to double the density of transistors on a chip every twoyears is becoming increasingly challenging. With scaling reaching its limit, manufacturers are looking to advanced packaging innovations to extend the performance gains that the industry, and the world at large, have grown to depend on. Cu-to-Cu hybrid bonding is one way the industry is looking to extend ever-increasing I/O density and faster connections, all while using less energy.
Not so long ago, Blu-ray was hailed as a technological advancement in the world of digital video. But in the streaming era, Blu-ray’s luster has faded. However, the technology responsible for the blue laser diode that gave the Blu-ray player its name – gallium nitride (GaN) – is emerging as one of a number of exciting new developments in the semiconductor industry.
Today, GaN is used by the military for radar systems, consumer and automotive electronics as a super-fast power charger and the telecommunications industry in base stations and data servers. GaN offers several advantages over silicon. For starters, GaN offers a significant increase in electron mobility over silicon – 1,000 times more electron mobility, according to various articles – a benefit that leads to other advantages. In addition, GaN is resistant to heat, consumes less energy than other semiconductors, operates at a lower voltage, enables increased miniaturization, offers wider bandwidth and allows for increased electron mobility.