Abstract
AI chiplet architectures are driving advanced IC substrates (AICS) toward larger panels, finer line/space, and much tighter overlay budgets. This study presents a lithography strategy that combines ultra-large exposure field and fine-resolution imaging with algorithmic early zone correction (EZC) to reduce alignment-solution errors, the largest item in the lithography overlay budget. In this study, we use overlay data from 510 x 515mm panel test vehicles to identify zone-level correctables and apply in-exposure pre-compensation. The approach reduces overlay errors in high-volume manufacturing, improving overlay by 38.2%. The methodology generalizes to ultra-high-density fan-out and 2.5D/3D packaging, providing a practical path to sustain overlay yield for next-generation AICS.
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Abstract
Fan-out panel-level packaging (FOPLP) offers significant advantages in meeting the aggressive demands of AI chips, particularly by supporting larger package sizes and optimizing substrate utilization. However, as the AI market continues to expand rapidly, the challenge lies in how to swiftly transition to mass production. A second challenge is yield; AI chips integrate multiple control units and high-bandwidth memory (HBM) during the packaging process. These components are expensive. Therefore, maximizing yield at every step and identifying defects early to minimize losses is critical. Yield prediction technology addresses both the speed and yield challenges of FOPLP lithography. This approach utilizes an offline metrology tool to measure die shifts or pattern distortions on the panel substrate. The metrology data is then analyzed using machine learning algorithms, which, when combined with customized process parameters, can accurately predict overlay errors and overlay yield. This predictive insight allows for more informed decision-making and earlier intervention in the lithography process. In this study, we will detail how yield prediction technology functions and how its application in the early R&D stages can accelerate development. We will also discuss how yield prediction technology can be implemented in mass production lines for pre-emptive quality control. With the expected significant growth of FOPLP over the coming years, we believe that yield prediction technology will provide a clear path toward achieving both rapid production and high yields in FOPLP lithography.
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Advanced IC substrates (AICS) have been marching toward the 2µm line/space (L/S) redistribution layer (RDL) technology node for some time (Figure 1). However, many questions remain about the ability of organic substrates to meet the line/space requirements of the next generation of advanced packages (AP), those below 2µm L/S and perhaps to 1.5µm L/S. Simply put: are organic substrates up to the challenge?
The answer to that has been no.
But with recent developments, the possibility of organic substrates reaching below 2µm appears to be changing.
Before we discuss the reasons why, we will first turn our attention to the core reasons organic substrates struggle with lower line/space requirements…
Panel-level advanced packaging technologies have been in development for more than a decade. They began as a way to reduce costs and improve yields for fan-out wafer level applications. Smartphone applications – particularly fingerprint sensors – promised the volumes that would make the investment successful.
However, memories of the fiasco of 450mm wafer efforts lived in the minds of many. Why make the investment in an ecosystem that may not demand high enough volumes to insure return on investment? Still, there were those who believed in the promise of panel-level packaging. Development efforts persevered, and PLP has moved through R&D and into pilot production. Still, through it all, many remained skeptical about there being high enough volumes to support it.
The Era of AI, coupled with the emergence of glass substrates, is set to change all that.
On September 30, 2024, I visited Onto Innovation’s headquarters in Wilmington, MA to attend the grand opening of its Packaging Applications Center of Excellence (PACE). The company has partnered with like-minded suppliers of the PLP ecosystem to accelerate the development of PLP technologies for both organic and glass substrates. These include 3D InCites Members: LPKF Laser & Electronics, Evatec, MKS-Atotech and Lam Research; as well as Resonac, Corning, and others.
The semiconductor industry is a land of peaks and valleys. It’s a place where each innovation represents the culmination of a long and often difficult climb to the summit. In the case of glass substrates, the peak of the mountain is in sight.
The arrival of glass substrates comes at an opportune time, as the industry eyes new process innovations to meet the incredible demand for high performance applications, like AI, and their stringent requirements, including further decreases in size and pitch for through glass vias (TGV). Up until now, organic substrates employed plated through hole (PTH) type vias , but these will be unable to meet these challenging requirements.
With the advent of glass core substrates replacing organic substrates, various processes hitherto requiring basic printed circuit board (PCB) technology take on a new dimension with significantly greater complexity. This blog discusses the formation of interconnects through the substrate, whether those interconnects are PTH for organic substrates or TGV in glass substrates.
Overlay is becoming a significant problem in the manufacturing of semiconductors, especially in the world of advanced packaging substrates — think panels — the larger the area, the greater the potential for distortion due to warpage. Solving this issue requires more accurate models, better communication through feed forward/feed back throughout the flow, and real-time analytics that are baked into the process. Keith Best, director of product marketing for lithography at Onto Innovation, talks with Semiconductor Engineering about the intricacies of overlay, the pros and cons of glass substrates, and what’s needed for high-volume manufacturing.
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