Yield Prediction Technology: A Game Changer for Cutting Costs and Reducing Ramp Time in FOPLP Lithography

Abstract

Fan-out panel-level packaging (FOPLP) offers significant advantages in meeting the aggressive demands of AI chips, particularly by supporting larger package sizes and optimizing substrate utilization. However, as the AI market continues to expand rapidly, the challenge lies in how to swiftly transition to mass production. A second challenge is yield; AI chips integrate multiple control units and high-bandwidth memory (HBM) during the packaging process. These components are expensive. Therefore, maximizing yield at every step and identifying defects early to minimize losses is critical. Yield prediction technology addresses both the speed and yield challenges of FOPLP lithography. This approach utilizes an offline metrology tool to measure die shifts or pattern distortions on the panel substrate. The metrology data is then analyzed using machine learning algorithms, which, when combined with customized process parameters, can accurately predict overlay errors and overlay yield. This predictive insight allows for more informed decision-making and earlier intervention in the lithography process. In this study, we will detail how yield prediction technology functions and how its application in the early R&D stages can accelerate development. We will also discuss how yield prediction technology can be implemented in mass production lines for pre-emptive quality control. With the expected significant growth of FOPLP over the coming years, we believe that yield prediction technology will provide a clear path toward achieving both rapid production and high yields in FOPLP lithography.