Over the past ten years, primarily driven by a tremendous expansion in the availability of data and computing power, artificial intelligence (AI) and machine-learning (ML) technologies have found their way into many different areas and have changed our way of life and our ability to solve problems. Today, artificial intelligence and machine learning are being used to refine online search results, facilitate online shopping, customize advertising, tailor online news feeds and guide self-driving cars. The future that so many have dreamed of is just over the horizon, if not happening right now.
The term artificial intelligence was first introduced in the 1950s and used famously by Alan Turing. The noted mathematician and the creator of the so-called Turing Test believed that one day machines would be able to imitate human beings by doing intelligent things, whether those intelligent things meant playing chess or having a conversation. Machine learning is a subset of AI. Machine learning allows for the automation of learning based on an evaluation of past results against specified criteria. Deep learning (DL) is a subset of machine learning (FIGURE 1). With deep learning, a multi-layered learning hierarchy in which the output of each layer serves as the input for the next layer is employed.
Currently, the semiconductor manufacturing industry uses artificial intelligence and machine learning to take data and autonomously learn from that data. With the additional data, AI and ML can be used to quickly discover patterns and determine correlations in various applications, most notably those applications involving metrology and inspection, whether in the front-end of the manufacturing process or in the back-end. These applications may include AI-based spatial pattern recognition (SPR) systems for inline wafer monitoring [2], automatic defect classification (ADC) systems with machine-learning models and machine learning-based optical critical dimension (OCD) metrology systems [1][7].
When the subject of hybrid bonding is brought up in the industry, the focus is often on how this technique is used to manufacture CMOS image sensors (CIS), an essential device for today’s digital cameras, particularly those found in smartphones. As such, CIS is a common touchpoint given the ubiquity of mobile phones, whether you hold a product from Apple, Samsung or Huawei in your hands.
But while today’s CIS devices currently dominate the use of hybrid bonding, high-performance computing (HPC) is emerging as a new high-growth application for hybrid bonding. This is a result of the trend toward finer pitched interconnects in advanced 3D packaged memory technologies. In addition, the market share of high-end performance packaging, including both 2.5D and 3D packaging, is expected to be $7.87B by 2027, with a compound annual growth rate (CAGR) of 19% from 2021 to 2027, according to Yole Développement. As for 3D stacked packaging alone, it is expected to grow at a CAGR of 58% to 70% during the same period.
Using direct Cu-to-Cu connections instead of bumps and suitable for pitches less than 10μm, hybrid bonding often involves the direct stacking of two wafers, with the space between the two planarized surfaces approaching zero. Hybrid bonding has advantages over conventional micro-bumping, such as enabling smaller dimension I/O terminals and reducing pitch interconnects. But while both hybrid bonding and conventional micro-bumping support higher-density interconnect schemes, hybrid bonding is an expensive process compared to bumping and requires much tighter process control, especially in the areas of defect inspection, planarity measurement and void detection.
While wafer-to-wafer bonding has already been demonstrated for NAND devices and is currently used in CIS manufacturing for the integration of the imager layer and logic, DRAM manufacturers are also looking to adapt hybrid bonding to replace bumps. Utilizing a hybrid bonding interconnect scheme capable of reducing the overall package thickness by tens and possibly hundreds of microns in certain situations, HBM (high-bandwidth memory) die are vertically stacked in 4,8,12,16 die stacks. The gap between each die is about 30μm when bumps are used, but the gap is nearly zero with hybrid bonding.
As 3D NAND continues to scale vertically — all in the name of increasing capacity and speed and reducing inefficiency and cost — maintaining channel hole critical dimension (CD) and shape uniformity becomes even more challenging. Faced with rising high-aspect ratios, addressing these challenges requires new inline non-destructive metrology to provide real-time process control. Infrared critical dimension metrology (IRCD) is one solution.
But while IRCD can be used to measure high-aspect ratio structures like the amorphous carbon hardmask and channel hole profile in 3D NAND, the mid-IR wavelength range can be used to measure non-memory devices like logic and CIS. In particular, IRCD can be a powerful metrology resource when it comes to detecting fluorinated polymer residue after cleans in advanced logic devices and measuring vertical doping concentration profiles after plasma doping in CIS.
The ability to trace the genealogy of all the components in an electronic device has been getting more complex for decades. For many industries — automotive, defense, medical and others — the need to locate the source of a problem in near real-time is paramount to gauging the extent of that problem. The extreme case is when the issue occurs with a product that already has been distributed and used in the field. Complicating matters is the fact that the current chip shortage is pushing chip designers to second- and third-tier suppliers for their inventory.
Tracking information is not easily done given the number of times material can change hands during the manufacturing life cycle. Designs can incorporate IP modules from Parties No. 1, No. 2, and No. 3 (figure 1). These designs are blended into a singular chip by the device’s Design House. This chip is then built at Front-end Foundries No. 1 or No. 2. The completed chip can be tested and partially assembled at OSAT A, B, or C. Finished assembly into a multi-chip module (MCM) or printed circuit board (PCB) can take place at Assembly House No. 1 or No. 2 (or happen at Customer A if they provide the IP for a design for a device that can be assembled by Finished Goods Maker No. 1) before it is finally sold by the Design House to the End User or Final Goods Manufacturer A, B, C, D and more for insertion in their end product, after which it is again tested before being sold to the end customer.
This is a very simplified example of how complex a supply chain can be, but it is illustrative nonetheless.
Virtual v. physical traceability
At some point in the supply chain, units receive a physical marker that enables traceability as it progresses through the remaining chain of manufacturing agents. Prior to the application of a marker, reliance on a part’s origin is a function of accounting and accurate recordkeeping. Although this seems simple enough, it is complicated by the transition of “ownership” of the chip as it moves through the supply chain.
Tracing a chip’s origin includes its transformation through multiple physical form factors. These material changes frequently include moving from a lot/wafer/die physical structure to a singulated die on a piece of tape or reel to an assembled die in a package, or in a tray, or as an inserted chip in a multi-chip module or PCB — ultimately ending with the PCB being inserted into a larger form factor, such as an automobile or a computer server. Each time the physical form factor is updated, there is a chance to break traceability in the supply chain if incoming and outgoing product labels are not meticulously documented. This is exacerbated by a lack of standardized data formats and communication frameworks throughout the supply chain. All too often, there is a gap in a unit’s back mapping. Once this occurs, any chance to trace a problem to a source is jeopardized.
In the leading high-volume manufacturing (HVM) process flows, materials-enabled scaling has increased inline applications for compositional metrology.
A previous blog discussed how Fourier transform infrared (FTIR) spectroscopy was used for inline composition measurements. These measurements informed advanced process control for the wafer-level processing of selectively etched 3D NAND wordlines and DRAM capacitor profiles.
FTIR metrology has further HVM applications, including incoming substrate quality assurance, hardmask selectivity qualifications in the middle of the line, and verification of Low-K porogen evolution during interlayer dielectric (ILD) depositions on the back end of the line. These examples illustrate how FTIR modeling delivers metrics based on materials’ bond types for compositional process control.
Vacuum based processes are essential in the semiconductor manufacturing process. In the simplest terms, integrated circuits are composite structures fabricated one layer at a time. Each layer is deposited as a blanket film, then patterned by removing material in selected areas. The final, three-dimensional structure, made up of insulating, conducting, and semiconducting components, forms a functional circuit. Most of the deposition and removal steps take place in a vacuum environment, which creates the physical conditions required for the process to proceed, ensures the purity of the material deposited, and removes excess process chemicals and by-products from the process chamber. Throughout its history, the semiconductor industry has defined progress almost exclusively by its ability to reduce the size of the devices it creates. Measuring critical dimensions of the component structures and controlling the manufacturing process to ensure high yields of functional devices have been a critical requirement for progress. These structures became too small to resolve with image based light microscopy decades ago. Manufacturers now rely on scatterometry for optical critical dimension (OCD) measurements. Because it is not image based, scatterometry is not constrained by the diffraction effects that limit image resolution. Furthermore, and especially important for current device architectures, scatterometry can provide three-dimensional measurements. In this article we will look at the fundamentals of OCD and provide some examples of its use on simple, representative structures.