You’ve read the reports: the memory market is floundering as the semiconductor industry moves through another scarcity/surplus cycle.
Be that as it may, innovation is happening as the industry continues to pursue increasingly higher three-dimensional stacks, with 3D NAND stacks taller than 200 layers entering production.
However, there are challenges. Among those: conventional optical critical dimension (OCD) metrology systems have difficultly measuring the tungsten (W) recess in the wordline (WL) slit following the replacement gate step. This is particularly a problem as high-aspect ratio (HAR) stacks reach 96 layers or higher. For manufacturers, the ability to measure the W recess is critical. Under-etching the W replacement gates in the recess can cause wordlines to short, while over-etching the W gates can damage cells or cause a short from the wordline to the source line.
Last summer, the semiconductor industry reached a significant milestone: one of the world’s top-tier fabs had begun production of the first 3D NAND chip with more than 200 layers. The announcement was significant but not a shock. Several other fabs had been progressing toward breaking the 200-layer barrier, so reaching the milestone was not a matter of if but when.
As significant as this advance is, the high-volume manufacturing challenges of producing high-aspect ratio (HAR) 3D NAND chips are considerable. One challenge is the ability to measure the tungsten (W) recess to the bottom of a 3D NAND device following the replacement gate process. Presently, there is no in-line process control solution that can accomplish this. The reason for this is known: beyond just a few layers in the stack, the W recess becomes opaque in the ultraviolet/visible/ near-infrared region, the realm of many OCD systems, after just a few layers in the HAR stack. Additionally, increased wordline slit pitch scaling further reduces the already minimal optical signal from the top of the 3D NAND structure to the bottom.
For decades, Moore’s Law has been a way to measure performance gains in the semiconductor industry, but the ability to double the density of transistors on a chip every twoyears is becoming increasingly challenging. With scaling reaching its limit, manufacturers are looking to advanced packaging innovations to extend the performance gains that the industry, and the world at large, have grown to depend on. Cu-to-Cu hybrid bonding is one way the industry is looking to extend ever-increasing I/O density and faster connections, all while using less energy.
Abstract
Ultrafast pump-probe measurements are used to characterize various samples, such as biological cells, bulk, and thin-film structures. However, typical implementations of the pump-probe apparatus are either slow or complex and costly hindering wide deployment. Here we combine a single-cavity dual-comb laser with a simple experimental setup to obtain pump-probe measurements with ultra-high sensitivity, fast acquisition, and high timing precision over long optical delay scan ranges of 12.5 ns that would correspond to a mechanical delay of about 3.75 m. We employ digital signal balancing to obtain shot-noise-limited detection compatible with pump-probe microscopy deployment. Here we demonstrate ultrafast photoacoustics for thin-film sample characterization. We measured a tungsten layer thickness of (700 ± 4) Å with shot-noise-limited detection. Such single-cavity dual-comb lasers can be used for any pump-probe measurements and are especially well-suited for ultrafast photoacoustic studies such as involving ultrasonic echoes, Brillouin oscillations, surface acoustic waves and thermal dynamics.
A mother steps on the brakes, bringing her car to a stop as she drops her kids off for dance lessons. At the time, she doesn’t notice anything wrong, but when she takes her car in for its regular service appointment, the mechanic conducts a diagnostic check and discovers that the primary brake system on the car had failed because of a faulty braking controller without anyone realizing it. Fortunately, the car was able to stop successfully due to the vehicle’s system redundancies, and the dealer’s diagnostic test confirms that since that first chip failure, another one has not occurred. The braking systems are behaving normally.
Following that, the dealership sends the information about the braking failure to the manufacturer, where an analyst notes that over the last 60 days, and around the country, six other brake failures traced back to the same controller system have been reported for the same make and model. In each of these situations, the backup system successfully brought each car to a complete stop. And, as in the case with the mother who dropped her kids off at dance class, the analyst looks at the reporting samples for these six other failures and determines that each is isolated and non-recurring.
As logic and memory semiconductor devices approach the limits of Moore’s Law, the requirements for accuracy in layer transfer become increasingly stringent. One leading silicon wafer manufacturer estimates that 50% of epitaxial wafer supply for logic will be on nodes equal to or less than 7nm. This is up approximately 30% from earlier in the decade.
To meet the demands of extreme ultraviolet (EUV) lithography, these leading-edge epi-deposited substrates have tighter specifications than previous substrates. Consider 3-5nm logic nodes: the image placement requirement can be as low as 3nm [1].
With the more stringent requirements of EUV lithography in mind, wafer makers are searching for new solutions, such as those addressing the primary reason for inaccuracies in image transfer: macro defects.