If you’ve been following the evolution of advanced packaging, you know that the industry is pushing boundaries like never before. From high-performance computing to industry-upending AI devices, the demand for smaller, faster, and more powerful chips is driving innovation at every level.
If you’ve been following the evolution of advanced packaging, you know that the industry is pushing boundaries like never before. From high-performance computing to industry-upending AI devices, the demand for smaller, faster, and more powerful chips is driving innovation at every level. One of the unsung heroes in this transformation: Glass carriers.
These carriers are becoming essential for applications involving high-bandwidth memory (HBM), 2.5D/3D integration, and chiplet architectures. During the manufacturing process, glass carriers serve as mechanical support for thin wafers and panel-level packages. Why? Glass carriers are noted for their warpage resistance, superior rigidity, and thermal stability. This combination of glass’ exceptional flatness and rigidity enables the precise placement of dies and interposers. Additionally, glass is optically transparent, which allows through-glass alignment during bonding and stacking, a critical capability for 3D integration where multiple layers must be accurately registered.
The benefits of glass carriers, however, come with several challenges, none of which should come as a surprise to anyone who has ever handled glass, whether in the fab or at home. Glass is fragile and, as such, is prone to surface defects, subsurface inclusions, and residual stress. Each of these can negatively impact die attachment quality, interconnect reliability, and die yield.
Let’s take a look at three major yield-killing culprits.
Surface defects such as particles, pits, and scratches are among the most common issues and may occur during glass carrier handling and processing, compromising the structural integrity and performance of advanced packaging assemblies (Figure 1). Particles can interfere with the bonding process, leading to poor adhesion or electrical discontinuities, while pits and scratches can propagate stress points that weaken the carrier during thermal cycling or molding.
However, subsurface inclusions and organic contamination, which are often introduced during reclaim or cleaning, pose more critical challenges. Inclusions within the glass can create localized stress concentrations, while organic residues can reduce UV transmission and cause bonding failures. These contaminants are particularly problematic in high-density interconnect environments where optical clarity and surface purity are critical.
Figure 1: Common glass carrier defects
In addition to surface and subsurface defects, residual stress represents a concern. Over time, these stress points, manifesting during thermal processing or mechanical handling, can lead to cracks or delamination, undermining the thermo-mechanical integrity of the entire package.
These potential challenges are compounded each time a glass carrier is reused in an effort to reduce overall packaging costs. Fortunately, technologies have been developed to address this obstacle. These technologies integrate AI-driven defect classification, real-time analytics, and adaptive scanning modes to maintain throughput without sacrificing accuracy, enabling manufacturers to detect surface anomalies, subsurface inclusions, and stress-induced defects with unprecedented precision.
Today’s wafer-based inspection platforms utilize laser scatterometry and imaging techniques to inspect for nanometer sized defects on a variety of opaque and transparent/semi-transparent substrates. These substrates may be suitable for either R&D or high-volume advanced IC substrate (AICS) and fan-out panel level processing (FOPLP) environments. Proprietary inspection technology with multiple detection channels and advanced signal processing algorithms is applied to achieve accuracy and reliability in glass carrier inspection.
Figure 2: Results of top (blue) and bottom (red) defect mapping.
With each channel optimized to capture unique scattering and reflection signatures, the technology differentiates between surface and subsurface defects, as well as stress-related anomalies, with remarkable accuracy. Surface particles, scratches, pits, bumps, surface contamination, film or bulk wafer stress, voids/inclusions can be detected, measured, characterized, and imaged. One of the most significant capabilities of this technology is the ability to conduct simultaneous top, bottom, and internal defect mapping, a critical need for transparent and semi-transparent substrates where defects can occur across multiple planes (Figure 2).
Beyond defect detection, Angstrom-level film thickness measurement provides precise control over surface coatings and residual layers. This capability is particularly valuable in the glass reclaim process where even minor variations in film thickness can impact UV transmission and bonding performance. By enabling accurate defect detection and grading, only glass carriers meeting stringent quality standards are returned to production.
By introducing technologies that mitigate risks by providing comprehensive defect mapping and stress analysis, manufacturers are able to maintain the mechanical and thermal integrity required for next-generation devices. This capability is especially valuable in markets such as AI devices, high-performance computing, and automotive electronics where reliability is non-negotiable. With this combination of advanced optical technology and robust algorithmic analysis, manufacturers can successfully achieve higher yields, lower costs, and greater confidence in their packaging processes.
As packaging complexity grows and the use of glass carriers increases, inspection systems that combine multi-depth defect mapping and stress analysis will become indispensable for ensuring yield and reliability in AI and HPC devices. With the explosive growth in AI-driven data centers and advanced packaging architectures, manufacturers need solutions that combine accuracy, speed, and cost efficiency. The laser-based wafer inspection technology discussed in this blog meets several glass carrier challenges head-on while enabling advanced packaging houses to maintain defect-free glass carriers in support of next-generation advanced packaging.
The future of glass carriers is clear: with the right technologies at the ready, manufacturers have the tools and the means to meet the growing needs of the AI and HPC markets.
Jason Lin is Director of Product Marketing at Onto Innovation.
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The FAaST system is a versatile, non-contact electrical metrology platform, with an option to combine micro and macro corona-Kelvin technologies together with digital surface photovoltage (SPV). It enables high-resolution dielectric and interface measurements across a wide range of dielectric materials, supporting both R&D and high volume manufacturing.
The primary application of non-contact CV metrology is monitoring dielectric properties during IC manufacturing. Unlike conventional electrical measurements, it requires no sample preparation, eliminating the need for MOS capacitor structures. This reduces metrology cost and enables fast data feedback in both R&D and manufacturing environments.
The corona-Kelvin method uses a corona discharge in air to deposit an electric charge (DQC) on the wafer surface. A vibrating Kelvin-probe then measures the resulting surface voltage (V), enabling determination of the differential capacitance (C= DQC/DV). By monitoring surface voltage in both dark and illuminated conditions, the system separates two key components: dielectric voltage (VD) and semiconductor surface potential (VSB), enabling determination of flat band voltage (VFB).
Analysis of the resulting charge-voltage data yields electrical parameters, including trap density (Dit), flat band voltage (Vfb), dielectric charge (Qtot), dielectric capacitance (CD), Equivalent Oxide Thickness (EOT), leakage current, and tunneling characteristics.
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The MBIR system is a revolutionary in-line, non-destructive infrared reflectometry system that enables critical process control of high aspect ratio structures, films and epitaxial structures. It meets the needs of leading-edge customers with its high speed and process coverage.
As more high aspect ratio processes are used in multiple industry segments, there are metrology needs for monitoring of related processes, including dimensions and properties of carbon film hard masks and etched 3D structures.
The MBIR system delivers high-throughput, low COO, non-contact, non-destructive measurements of dimensions and uniformity of layers and etched structures used in integrated circuit manufacturing. The small spot size makes the tool suitable for measurements of scribe line test structures as in-line process control. The unique technology and analysis capability simplifies system calibration requirements and removes the effect of substrate variations for key layer measurements.
While the software contains advanced features for measurement recipe and analysis model creation, it has a user-friendly interface and implementation that allows the fab customers to create and manage the recipe system for MBIR tool fleets.
Thickness map from amorphous carbon film
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The FAaST Digital SPV system provides a fast, non-contact, and preparation-free method for full wafer imaging of contamination in silicon. High resolution maps of diffusion length and iron (Fe) concentration are generated in minutes, setting the industry standard for precision and sensitivity in Fe contamination control, reaching the E7 cm-3 range.
There is no disputing the detrimental effect of metallic contamination on the integrity of the critical gate oxide used in integrated circuits. During high temperature processing, contamination in the silicon wafer often precipitates at the Si/dielectric interface or segregates into the dielectric—both scenarios can cause premature device failure and reduced yield. As device dimensions shrink, the tolerance for contamination decreases, requiring ever-lower background levels of metals like iron (Fe). Over the past 25 years, the IC industry has reduced typical Fe concentrations by more than three orders of magnitude, yet further reduction is essential, especially for applications like CMOS image sensors.
The FAaST Digital SPV system addresses this challenge with industry-leading sensitivity and speed. It provides a fast, non-contact, and preparation-free method for full-wafer imaging of contamination. High-resolution maps of minority carrier diffusion length and Fe concentration are generated in minutes, enabling fabs to detect and control contamination at levels as low as the E7 cm⁻³ range.
Figure 1. Typical background Fe concentration in new IC Fablines (blue) and the state-of-the-art SPV detection limit (red)
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The Atlas G6 system is an OCD and thin film metrology tool engineered for the most advanced logic and memory devices. Designed to meet the demands of next-generation AI applications and beyond, it delivers enhanced optics, AI-driven recipe development, and tighter tool matching for superior process control.
As semiconductor manufacturers push into next-generation GAA nodes and next-gen HBM and vertical DRAM architectures, process control requirements are tightening. Smaller nanosheet structures and denser DRAM cells demand higher measurement precision, faster recipe development, and tighter tool-to-tool matching.
The Atlas® G6 system is engineered to meet these challenges with a new optics design that improves signal-to-noise ratio, spectral stability, and measurement precision. Enhanced software algorithms and data management tools deliver better fleet-wide spectra matching, while a new data channel and next-generation model-guided machine learning in Ai Diffract™ software enable faster, more robust recipe development. A smaller optical spot size ensures accurate measurements on today’s most compact DRAM structures.
Fully integrated with Onto Innovation’s Discover® ecosystem, the Atlas G6 system empowers fabs with predictive process control and smart manufacturing capabilities—accelerating yield and time to market for the industry’s most advanced devices.
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The demand for high bandwidth memory (HBM) is accelerating across the semiconductor industry, driven by boundary-pushing artificial intelligence, high-performance computing, and advanced graphics. These technologies require access to vast datasets, which in turn increases the need for memory solutions that combine speed, density, and power efficiency. HBM meets these demands by vertically stacking memory dies and linking them with ultra-fast interconnects.
With data rates rising, the need for increased output contact pad density is needed. To address this, bump technologies are being pushed beyond what was previously thought to be their physical and performance limits. As it stands today, some memory designers are innovating their way to bump sizes below 10µm in high volume manufacturing. Be that as may, scaling bump height to 2μm will be considerably challenging, leading some to explore hybrid bonding as an interconnect solution.
Hybrid bonding enables finer interconnect pitches of less than 10μm, allowing for more I/O terminals in a smaller area. This increased density translates directly into higher bandwidth and improved overall performance.
Traditional bump-based stacking introduces gaps of about 30μm between dies, while hybrid bonding offers direct Cu-to-Cu connections. By achieving near-zero spacing between dies, hybrid bonding significantly reduces overall package thickness and offers lower resistance and better thermal conductivity than bump-based methods. The result: improved signal integrity, reduced power consumption, and enhanced heat dissipation, each of which are critical for HBM.
Finally, hybrid bonding supports several configurations: wafer-to-wafer, die-to-wafer, and die-to-die, offering flexibility in manufacturing and integration. This adaptability is vital for scaling HBM technologies across different applications and performance tiers.
Of course, hybrid bonding offers manufacturers its own set of challenges—increased sensitivity to particles and organic residues, lower yields and introduction of more costly process and process control steps—making the decision to stick to the tried-and-true microbump technology over the emerging, innovation a debate worth having.
In this two-part blog series, we will compare these two interconnect solutions and discuss the challenges they face (Figure 1).
Figure 1: Interconnect challenges in microbump and hybrid bonding technologies.
Bumps have several advantages over hybrid bonding. As a mature technology, they are widely used and well-understood in the industry. They are also compatible with existing flip-chip and underfill processes, and are scalable for moderate density. In addition, the cost of bump technologies is lower than hybrid bonding technologies.
However, microbumps have a number of disadvantages compared to hybrid bonding. The most significant of which are the pitch limitations of bump technologies. Microbumps struggle at pitches below 10µm due to challenges in plating uniformity and solder reflow. Bumps also require underfill, which can introduce stress and complicate thermal management.
Limitations aside, bump technology continues to evolve. Leading suppliers of bump plating systems project a continued downscaling of bump dimensions, with diameters decreasing to the 5µm to 4µm range and heights dropping as low as 2µm to 1µm. At a 10µm pitch, the lateral footprint remains sufficient to support the high-density I/O requirements of advanced memory architectures. Concurrently, the reduced bump height enables vertical integration of up to 16 stacked HBM dies within the 775µm maximum package height defined by Joint Electron Device Engineering Council (JEDEC) standards. Consequently, bump interconnects remain a viable and scalable solution for next-generation HBM, and major manufacturers are maintaining substantial R&D investments in bump technology.
Hybrid bonding, while promising, presents its own set of challenges. Chief among them, hybrid bonding is especially sensitive to particles and organic residues; for example, even 1µm particles can cause defects. These residues can prevent proper contact, trap gases or moisture, and lead to void formation during bonding. Voids can cause delamination or incomplete bonding, reducing mechanical integrity and electrical continuity. Hybrid bonding also is more expensive than traditional bump technologies and may require manufacturers to purchase new equipment and adopt new process flows before moving away from bump technology.
As demand for HBM intensifies, the industry stands at a crossroads in interconnect technology. While microbumps have evolved to support increasingly dense and tall HBM stacks, they face several obstacles. Hybrid bonding offers a compelling alternative, but not without its own hurdles. Ultimately, both technologies are advancing in parallel, each with unique strengths and limitations.
Regardless of which interconnect technology is chosen, a comprehensive suite of interconnect solutions will be needed to address the obstacles manufacturers of HBM devices face. In the second in this two-part series, we will explore a number of these solutions that, when combined, tackle the biggest challenges facing interconnects in HBM.
Damon Tsai joined Onto Innovation in 2018 and has extensive experience in inspection and metrology, with a specialized focus on semiconductor FEOL, advanced packaging, OSAT, and specialty markets like RF, Power, and CIS. He currently serves as the Senior Director of Product Marketing, Inspection.
Woo Young Han joined Onto Innovation in 2000 and is currently Product Marketing Director, Inspection. He holds an Electrical Engineering degree from University of Toronto.
Tim Kryman is Product Marketing Senior Director, Metrology and Inspection. Tim has been with Onto Innovation for more than 20 years and holds a BS in Accounting and Information Systems from Lock Haven University and an MBA from DeSales University.
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