Advanced IC substrates (AICS) have been marching toward the 2µm line/space (L/S) redistribution layer (RDL) technology node for some time (Figure 1). However, many questions remain about the ability of organic substrates to meet the line/space requirements of the next generation of advanced packages (AP), those below 2µm L/S and perhaps to 1.5µm L/S. Simply put: are organic substrates up to the challenge?
The answer to that has been no.
But with recent developments, the possibility of organic substrates reaching below 2µm appears to be changing.
Before we discuss the reasons why, we will first turn our attention to the core reasons organic substrates struggle with lower line/space requirements…
In the semiconductor industry, digital twins are the focus of a lot of attention, with substantial investments from industry players and governments alike. This year the European Union and the United States have pledged hundreds of millions of dollars in grants and funding opportunities, including the new CHIPS Digital Twin Manufacturing USA Institute. Ultimately, many people see great value in innovating, commercializing and scaling digital twin technology.
As with many trends, digital twins are the subject of speculation and fervor. Unfortunately, this enthusiasm can drive well intentioned users and organizations to choose solutions they don’t need – or spend too much time and money before arriving at reliable ones.
Panel-level advanced packaging technologies have been in development for more than a decade. They began as a way to reduce costs and improve yields for fan-out wafer level applications. Smartphone applications – particularly fingerprint sensors – promised the volumes that would make the investment successful.
However, memories of the fiasco of 450mm wafer efforts lived in the minds of many. Why make the investment in an ecosystem that may not demand high enough volumes to insure return on investment? Still, there were those who believed in the promise of panel-level packaging. Development efforts persevered, and PLP has moved through R&D and into pilot production. Still, through it all, many remained skeptical about there being high enough volumes to support it.
The Era of AI, coupled with the emergence of glass substrates, is set to change all that.
On September 30, 2024, I visited Onto Innovation’s headquarters in Wilmington, MA to attend the grand opening of its Packaging Applications Center of Excellence (PACE). The company has partnered with like-minded suppliers of the PLP ecosystem to accelerate the development of PLP technologies for both organic and glass substrates. These include 3D InCites Members: LPKF Laser & Electronics, Evatec, MKS-Atotech and Lam Research; as well as Resonac, Corning, and others.
On September 30, 2024, Onto Innovation held the grand opening of its Packaging Applications Center of Excellence – or as it’s being called, PACE. Françoise von Trapp attended the grand opening to learn why the company has partnered with like-minded suppliers of the panel-level packaging ecosystem to accelerate the development of PLP technologies for both organic and glass substrates. These include 3D InCites Members: LPKF Laser & Electronics, Evatec, MKS-Atotech and Lam Research; as well as Resonac, Corning, and others.
This episode starts off with a conversation with Onto Innovation CEO, Mike Plisinski, who explains how PACE came to be, its business model, and why AI is driving growth in panel-level packaging.
The story continues with a tour of PACE conducted by Keith Best, Director of PACE. Best gives a step-by-step description of the processes as panels move from the photoresist coater, to the lithography stepper, to the developer, and then to the inspection system. He also talks about the role advanced lithography tools play in developing down-stream panel level processes.
Lastly, you’ll hear from PACE collaboration partners:
- Ralph Zoberbier, CMO, Evatec
- Kuldip Johal, MKS-Atotech
- Kazuyuki Mitsukura, Resonac
- Junro Yoon, Corning Advanced Optics
- Richard Noack, LPKF Laser & Electronics
The semiconductor industry is a land of peaks and valleys. It’s a place where each innovation represents the culmination of a long and often difficult climb to the summit. In the case of glass substrates, the peak of the mountain is in sight.
The arrival of glass substrates comes at an opportune time, as the industry eyes new process innovations to meet the incredible demand for high performance applications, like AI, and their stringent requirements, including further decreases in size and pitch for through glass vias (TGV). Up until now, organic substrates employed plated through hole (PTH) type vias , but these will be unable to meet these challenging requirements.
With the advent of glass core substrates replacing organic substrates, various processes hitherto requiring basic printed circuit board (PCB) technology take on a new dimension with significantly greater complexity. This blog discusses the formation of interconnects through the substrate, whether those interconnects are PTH for organic substrates or TGV in glass substrates.
The concept of zero defect manufacturing has been around for decades, arising first in the aerospace and defense industry. Since then, this manufacturing approach has been adopted by the automotive industry, and it has only grown in importance as the sector transitions to electric vehicles. Given the role semiconductors play in today’s vehicles, and will play in the future, it is no surprise the industry has adopted a zero defect approach.
However, the quest for zero defect manufacturing goes well beyond the aerospace, defense, and automotive industries. Many companies that have started or are planning digital transformations are pursuing zero defect manufacturing. Accomplishing this requires using data from a wide range of sources, including materials, products, processes, factory subsystems, and equipment. When all of this data is properly integrated, and fabs are able to take complete advantage of the analytics from their monitoring systems, the goal of a zero defect manufacturing environment is achievable.
Before we go any further, we should get one thing out of the way: zero defect manufacturing does not promise zero defects. It is a commitment to properly identifying defects and sources, giving manufacturers the opportunity to detect dormant failures early on and make proactive corrections.