The growing demand for heterogeneous integration is driven by the 5G market that includes smartphones, data centers, servers, HPC, AI and IoT applications. Next-generation packaging technologies require tighter overlay to accommodate a larger package size with finer pitch chip interconnects on large format flexible panels.
Fan-out panel level packaging (FOPLP) is one of the technologies that is able to achieve market requirements, but also faces several signification processes challenges. One critical challenge for FOPLP is die placement error, which is a result of the reconstitution process. Die placement error can cause high overlay error, which induces low overlay yield. To address this situation, site by site correction exposure with feedforward lithography is proposed. Site by site correction exposure can overcome the die placement error to achieve an acceptable overlay yield, and feedforward lithography is used to improve the throughput when using site by site correction exposure. An issue was observed when using feedforward site by site correction method: when one or more reconstituted dies suffered large displacement error, these large error dies affect the correctable accuracy of the site and induce poor overlay to all the dies in the site. To address this issue, which could induce poor overlay, advanced outlier control technology is proposed. Advanced outlier control technology is used for identifying the large error dies and processing these large error dies to prevent the situation.
In this paper, we demonstrated advanced outlier control technology with feedforward lithography on a selected test vehicle, which is a 510 mm x 515 mm panel. 400 simulation dies were built on this panel and part of the dies were designed with a large displacement error. The panel was processed using advanced outlier control technology with feedforward lithography in the demonstration. This demonstration showed how these two technologies integrated together and how this integration strategy worked for the FOPLP process. We also review and discuss the results for how this integration technology can maintain yield and throughput under such challenging conditions.
The growing demand for heterogeneous integration is driven by the 5G market that includes smartphones, data centers, servers, HPC, AI and IoT applications. Next-generation packaging technologies require tighter overlay to accommodate a larger package size with finer pitch chip interconnects on large format flexible panels.
Heterogeneous integration enables next-generation device performance gains by combining multiple silicon nodes and designs inside one package. The package size is expected to grow significantly, increasing to 75 x 75 mm and 150 x 150 mm, within the next few years. For these requirements, an extremely large exposure field with fine resolution lithography will enable packages well over 250 x 250 mm without the need for image stitching while exceeding aggressive overlay and critical uniformity requirements for these packages.
The lithography challenge to fulfill the need of heterogeneous integration is the limitation of exposure field size of the currently available solutions in the market. Multiple shots with stitching is used and this affects not only productivity performance but potential yield loss at the stitching boundary. Addressing the critical lithography challenges described above becomes an important task in heterogeneous integration, and an extremely large exposure field with fine resolution lithography is one of the best solutions for this task.
In this paper, a 515 mm x 510 mm panel is selected as the test vehicle, and we will demonstrate an extremely large exposure field with fine resolution technology on this panel. This demonstration provides the results and details about how this new technology will address the challenges of large package size processes.
When it comes to multi-chip module (MCM) manufacturing, fan-out wafer-level and fan-out panel-level packaging have received a lot of coverage recently. Every week, it seems like there is an announcement about “Company XYZ” moving their products into the fan-out wafer-level packaging (FOWLP) or fan-out panel-level packaging (FOPLP) space. But these moves come with challenges that didn’t exist in the advanced packaging assembly space years ago. And it’s these challenges that today’s MCM manufacturers need to address.
Consider this: at the most ambitious panel manufacturing facilities, masking layers may now number a dozen or more layers. Couple that with the fact that there may be more than 60 days of cycle time at some FOWLP facilities, and it becomes clear that the issues MCM factories need to address are looking similar to the issues front-end (FE) fabs faced in the 1980s.
Back then, FE operations drove many of the requirements — from factory automation to data collection and analytics — that we take for granted in today’s semiconductor industry.
The reasons why defect and yield management systems were important to fabs in the 1980s are the same reasons defect and yield management systems are needed now at MCM factories. This holds true for die-first fan-out wafer-level manufacturing and die-last fan-out panel-level manufacturing.
When it comes to FOWLP manufacturing, the operational processes are similar to the operational processes used in semiconductor manufacturing, with lithography, film deposition and etching all playing roles. The two manufacturing environments have several common steps, film etching and polishing being the most obvious. Much like the FE, these MCM tools need dynamic controls and run-to-run management in order to properly function, day in and day out. These facilities can leverage the lessons that have been learned from decades of excursion events and ever faster yield ramps in FE fabs by including integrated metrology defect and yield systems during the initial MCM facility build out.
The following paper presents a case study describing how to improve yield and fab productivity by implementing a frequent pattern database that utilizes Artificial Intelligence based Spatial Pattern Recognition (SPR) and wafer process history. This is important because associating spatial yield issues with process and tools is often performed as a reactive analysis, resulting in increased wafer scrap or die loss that could be prevented. The implementation of fab fingerprint technology proactively generates a pareto of high impacting process steps and tools based on a pattern score, enabling the production team to concentrate more efficiently on yield limiting events.
Analysts are projecting strong growth in advanced packaging, with CAGR through 2026 approaching 7% across the segment; much higher for certain high-end technologies, including 3D stacking, embedded die, and fan-out. Outsourced assembly and test (OSAT) firms, which package finished die manufactured by independent device manufacturers (IDM) and foundries, will be challenged by the complexity of the advanced packaging processes and will face stiff competition, in many cases from their own customers. If they are to thrive, or perhaps just survive, they will need to embrace smarter manufacturing approaches.
The historical division between front-end device manufacturing and back-end packaging/testing is the result of their vastly different cost structures and process complexity. The relative simplicity of the back-end process led OSATs to compete primarily on price, seeking always to minimize costs and maximize volume. Simple processes were simple to control. The acquisition, storage, and analysis of process data were costs to be avoided wherever possible. Advanced packaging processes have introduced a host of new variables that must be controlled to ensure process yield and product reliability. Process data is no longer a cost to be avoided, but should be considered an essential asset to be leveraged to maximize profitability.
Meanwhile, as they accommodate increasingly complex processes, OSATs confront encroachment in their markets by sophisticated competitors who may also be their customers – IDMs and foundries who have outsourced a significant portion of their production to OSATs but have also maintained their own internal back-end capabilities. Advanced packaging processes have been described as the migration of front-end like processes to traditionally back-end applications. With this evolution, the advantage device manufacturers once had, by outsourcing assembly and test to avoid diluting their expertise with low-value processes, has greatly diminished. More importantly, these customers-turned-competitors are already comfortable with managing complex processes – they wrote the book. In addition to IDMs and foundries, substrate and printed circuit board (PCB) suppliers, electronic manufacturing services (EMS), original design manufacturers (ODM), and others see the opportunity presented by the significant growth forecasted for advanced packaging.
Data is the life blood of smarter manufacturing – acquiring it, storing it, organizing it, analyzing it, sharing it. Without leveraging it you are not just blind; in the competitive environment of semiconductor manufacturing, you will probably not survive. OSATs are not new to data collection and management. After all, testing is part of their name. But test data is product/function focused. In its simplest form it is go/no go. Functional testing may go beyond that, to measure how well it works, if for no other reason than to identify the best devices and sell them for premium prices. Smarter manufacturing requires data on a whole new scale – data that is both deep and broad.
In their continuing drive to pack more computing power and speed into less space, semiconductor manufacturers are using advanced packaging (AP) processes to integrate multiple die of different types within a single package and to increase input/output (I/O) connectivity for large, complex chips. The use of front-end-like processes to create ever smaller features on ever larger substrates is increasing the need for process control and inspection in AP processes. Novel materials like organic polymer dielectrics pose special challenges to conventional front-end optical technologies. Our new illumination technology, Clearfind®, specifically addresses these issues to provide high-sensitivity defect detection.
Packaging evolution
Packaging processes have evolved from relatively simple, inexpensive technologies to costly, complex processes that have adopted and adapted process technologies developed for wafer fabrication. Some of these processes are discussed in the sections below.
Wire bonding. Traditionally, packaging uses thin wires bonded between I/O pads at the edge of the chip and a wire frame that includes pins for connection to a printed circuit board. The chip and frame are encapsulated for protection from the external environment, resulting in a final package that is much larger than the chip.
Flip chip. Chip-scale processes, like flip chip, form contact pads on the top surface of the die, which, when the separated die are flipped over, mate with solder balls on a connecting package substrate. Flip-chip packages allow many more I/O connections because the entire surface of the chip, not just the edges, can be used for contacts. The resulting package is smaller than wire bonding, but usually larger than the chip.
Wafer-level processing. Wafer-level processing (WLP) uses front-end-like processes to form packaging structures on chips while they are still part of the wafer on which they are fabricated. WLP has the benefit of creating small packages – the same size as the chip – but that small size ultimately limits the space available for I/O connections.
Fan-out wafer-level processing. Fan-out wafer-level processing (FOWLP) offers increased I/O capability. Separated chips are embedded in a round substrate with space added between the chips. Overlying redistribution layers (RDL) route signals from contacts on the top surface of the chip to contacts on the top surface of the larger substrate extending beyond the area of the chip itself. The round, wafer-like form factor of the reconstituted FOWLP substrates permits the use of process equipment and handlers designed for wafer processing with minimal modification. But it also limits the size of the substrate (and therefore the number of die that it can contain), and it wastes space near the curved edges of the substrate where rectangular die/packages do not fit efficiently.
Fan-out panel-level processing. Fan-out panel-level processing (FOPLP) is similar to FOWLP except the panel substrates are not limited to wafer-like form factors. They can be rectangular, to increase spatial efficiency, and larger, to process more die per panel at lower cost per die.