Abstract

The growing demand for heterogeneous integration is driven by the 5G market. This includes smartphones, data centers, servers, high-performance computing (HPC), artificial intelligence (AI) and internet of things (IoT) applications. Next-generation packaging technologies require tighter overlay to accommodate larger package sizes with fine-pitch chip interconnects on large-format flexible panels. Heterogeneous integration enables device performance gains by combining multiple silicon nodes and designs inside one package. The package size is expected to grow significantly, increasing to 75mm x 75mm and 150mm x 150mm, within the next few years. For these requirements, an extremely large exposure field fine-resolution lithography solution was proposed to enable packages well over 250mm x 250mm without the need for image stitching, while exceeding the overlay and critical uniformity requirements for these packages.

One of the challenges of extremely large exposure field fine-resolution lithography is to achieve an aggressive overlay number. Formation changes experienced by the panel as a result of thermo, high-pressure and other fan-out processes shift the design location from nominal coordinates; this causes inaccurate overlay and low-overlay yield in the lithography process. Addressing this critical lithography challenge becomes an important task in heterogeneous integration.

In this paper, a 515mm x 510mm Ajinomoto build-up film (ABF)+copper clad laminate (CCL) substrate is selected as the test vehicle. We will analyze the pattern distortion of an ABF+CCL substrate to understand the distribution of translation, rotation, scale, magnification, trap, orthogonality and other errors in the substrate, and then use extremely large exposure field fine-resolution lithography to address the pattern distortion of the substrate. This demonstration will provide an analysis of panel distortion and detail how the extremely large exposure field fine-resolution lithography solution addresses panel distortion to achieve an aggressive overlay number.

As technology nodes shrink, end users are designing systems where each chip element is being targeted for a specific technology and manufacturing node. While designing chip functionality to address specific technology nodes optimizes a chip’s performance regarding that functionality, this performance comes at a cost: additional chips will need to be designed, developed, processed and assembled to make a complete system solution.

At back-end packaging houses in the past, a multi-chip module (MCM) placed various packaged chips on a printed circuit board. Today in the advanced packaging space, fabless companies are using an Ajinomoto build-up film (ABF) substrate as a method of combining various chips into a smaller form factor. As the push for increased density in smaller multi-chip module packages increases, process cost increases as well. Along with rising costs, the cycle times needed to process ABF substrates with ever more redistribution layers (RDL) also increases. Consequently, the need for back-end packaging houses to maintain process control and detect defects is going to be similar to what front-end fabs encountered in the 1990s.

Currently, substrates are 100µm to 150µm thick. As with front-end semiconductors, Moore’s law is going to come into play with advanced substrate packaging technology. Line width/interconnects are going to shrink, and the need to be able to control and detect feedback will grow.

Reticle exposure on a non-ridged substrate inherently will require better control for rotational, scaling, orthogonal and topology variation compensation. One solution is to use a feed-forward adaptive-shot technology to address process variations, die placement errors and dimensionally unstable materials. Such a solution uses a parallel die-placement measurement process, while advanced analytics provide a means to balance productivity against yield.

Displacement errors can be measured on a lithography tool, but the measurements are slow, typically taking as much time to conduct as the exposure. But moving the measurements to a separate automated inspection system and feeding those corrections to the lithography system can double throughput. In addition, yield software adds predictive yield analysis to the externally conducted measurement and correction procedures and increases the number of die included in the exposure field up to a user-specified yield threshold.

Ajinomoto build-up film (ABF) substrate has been a key component in chip manufacturing since its introduction shortly before the turn of the millennium. Substrates made with Ajinomoto build-up film – an electrical insulator designed for complex circuits – are found in PCs, routers, base stations, and servers.

Looking ahead, the ABF substrate market will continue to grow, with revenue up last year due to the strong demand for 5G, high-performance computing (HPC), servers and graphic processing units (GPU), as well as from the automotive industry. According to Goldman Sachs, the total demand for the ABF market should maintain a CAGR of 28% from 2022 to 2025. Like so many other essential components in the global supply chain, there is a shortage of ABF substrates.

But rising demand and supply chain issues aren’t the only factors contributing to the shortage of ABF substrates. Larger package sizes and an increasing number of layers for these high-technology products also play a part; after all, these larger packaging sizes result in fewer packages per ABF substrate. And since the manufacturing of ABF substrate is a build-up layer process, a defect in any one layer can hamper the final yield of the entire substrate. Given these factors facing the ABF substrate market, yield control becomes even more important than it was before.

FAN-OUT PANEL LEVEL PACKAGING (FOPLP) has multiple benefits in advanced packaging applications, including enhanced connectivity and reduced costs. FOPLP differs from wafer-level packaging processes in that FOPLP utilizes large, rectangular panels rather than the round silicon wafers typically associated with IC manufacture. FOPLP’s rectangular panels more efficiently fit rectangular die, which can reduce costs since manufacturers can process more packages in each run.

Despite many advantages, FOPLP also faces specific challenges, such as yield loss caused by inaccurate die placement and the resulting overlay errors. In this context, dies with unusually large placement errors, or outliers, can be especially troublesome. These outliers cause losses of both the misplaced die and surrounding dies. However, integrating outlier control with feedforward metrology can greatly improve both yield and throughput.

Fan-out processes cut individual dies from the wafer and reconstitute them on a processing substrate separated by additional space. Subsequent steps fabricate redistribution lines in multiple layers and end with the creation of contacts on the surface of the package. The area available for contacts is increased by the additional space between chips, allowing more contacts per chip.

One critical challenge for FOPLP is die-placement error. This error originates during the robotic pick-and place operation in which chips are positioned on the reconstitution substrate. The problem arises when die positions shift during subsequent processing steps. If uncorrected, these die-placement errors can result in overlay errors and reduced yield. While die-placement errors can be measured and corrected, die-by-die in the lithography tool, this greatly reduces throughput. Feedforward lithography, which measures placement errors and calculates corrections in a separate system and then feeds the corrections forward to the lithography system is much faster. Lithography throughput can be further increased by including more than one die in each exposure site and then applying site-by site corrections to the exposures.

In this scheme, dies with unusually large placement errors can have an outsized impact on yields by skewing the site correction to such a degree that the site correction causes unacceptable overlay errors for all dies in the site. A solution: advanced outlier control technology (Figure 1). This technology detects outliers and excludes them from the correction calculation, thereby sacrificing the outlier to optimize overall yield and throughput.

The ability to trace the genealogy of all the components in an electronic device has been getting more complex for decades. For many industries — automotive, defense, medical and others — the need to locate the source of a problem in near real-time is paramount to gauging the extent of that problem. The extreme case is when the issue occurs with a product that already has been distributed and used in the field. Complicating matters is the fact that the current chip shortage is pushing chip designers to second- and third-tier suppliers for their inventory.

Tracking information is not easily done given the number of times material can change hands during the manufacturing life cycle. Designs can incorporate IP modules from Parties No. 1, No. 2, and No. 3 (figure 1). These designs are blended into a singular chip by the device’s Design House. This chip is then built at Front-end Foundries No. 1 or No. 2. The completed chip can be tested and partially assembled at OSAT A, B, or C. Finished assembly into a multi-chip module (MCM) or printed circuit board (PCB) can take place at Assembly House No. 1 or No. 2 (or happen at Customer A if they provide the IP for a design for a device that can be assembled by Finished Goods Maker No. 1) before it is finally sold by the Design House to the End User or Final Goods Manufacturer A, B, C, D and more for insertion in their end product, after which it is again tested before being sold to the end customer.

This is a very simplified example of how complex a supply chain can be, but it is illustrative nonetheless.

Virtual v. physical traceability

At some point in the supply chain, units receive a physical marker that enables traceability as it progresses through the remaining chain of manufacturing agents. Prior to the application of a marker, reliance on a part’s origin is a function of accounting and accurate recordkeeping. Although this seems simple enough, it is complicated by the transition of “ownership” of the chip as it moves through the supply chain.

Rapidly growing demand for new types of functionality across an expanding range of applications, including 5G communication, smartphones, data centers, servers, high- performance computing (HPC), artificial intelligence (AI) and the Internet of Things (IoT), is driving a fundamental shift in the way electronic devices are designed and manufactured. Gone are the days when advances were defined by an increasing number of shrinking transistors with ever-faster switching times and lower power consumption, all fabricated as a single, monolithic integrated circuit (IC). Many of today’s most advanced systems integrate multiple die, each optimized for a specific capability and fabricated with a process designed specifically for that type of circuit. These disparate chips are then connected using advanced packaging (AP) technologies, a process known as heterogeneous integration (HI).

One example of HI uses advanced IC substrates (AICS) in a process known as ultra-high density (UHD) panel fan-out. This fan-out panel level process (FOPLP) is a  redistribution lines (RDL)-first approach, where many layers of patterned conductive and insulating material are processed on both sides of a large panel to route electrical signals between the integrated chips, which are added last. Once the RDL layers are complete, solder bumps are added to form connection points that will mate with matching connection pads on the component ICs. Package substrate sizes are expected to reach 150mm x 150mm in the next few years. Panels, which may be 500mm x 500mm or larger, can accommodate many more packages per panel than the substrates used in wafer-level processes, which are restricted to round, wafer-like substrates of 300mm or less in diameter.

The lithography challenge for large heterogeneous integration is the limited size of the exposure field (typically 60mm x 60mm or less) for most currently available lithography systems. Smaller-field systems can be used to pattern large substrates by stitching together multiple exposures, but this affects both productivity and yield because of the need for multiple exposures of multiple reticles and the risk of errors at the stitching boundaries. A large exposure field would eliminate these impediments. However, there are also challenges associated with a large exposure field. These include panel warpage and distortion, which can impact critical dimensions, uniformity and overlay.

We describe here the use of our large-field lithography system (JetStep® X500) to expose 250mm x 250mm substrates in a single shot on 515mm x 510mm panels. Our evaluation included: 1) critical dimension (CD) control for 3m, 5µm and 6µm lines/spaces, and 15μm and 20μm vias; 2) CD uniformity across the exposure field; and 3) overlay accuracy. We used copper clad laminate (CCL) and Anjinomoto build-up film (ABF) panels for resolution, and glass panels with liquid resist for overlay and uniformity. The large field eliminates stitching, allows the exposure of more large package substrates in a single shot and requires fewer shots to complete a panel. We compares the exposure layout for a large field (250mm x 250mm) and a smaller field (59mm x 59mm) on a 510mm x 515mm panel. With the large exposure field, the panel can be completely exposed with just four shots, while the smaller field requires 64 shots.