Metrology Challenges in Advanced Packaging: Focus on Die-to-Die and Die-to-Wafer Bonding

Abstract

As advanced packaging technologies evolve to support heterogeneous integration, approaches such as 2.5D/3D IC integration, Co-Packaged Optics (CPO), High Bandwidth Memory (HBM), System-on-Integrated-Chip (SOIC), and Through-Silicon Vias (TSVs) have emerged as key enablers of high-bandwidth, low-power interconnects. These architectures introduce complex process integration challenges—particularly in die-to-die and die-to-wafer bonding—that place stringent demands on metrology for process control, yield management, and long-term reliability. This presentation examines metrology requirements across critical process steps in die-to-die and die-to-wafer bonding, with a focus on:
• Bonding interface integrity, where Cu dishing, film thickness variation, voids, and delamination can lead to early reliability failures.
• Alignment and warpage control, where sub-micron die placement accuracy and die warpage directly impact optical coupling and electrical interconnect fidelity.
• TSV dimensional control, including via depth, critical dimension (CD), and top/bottom alignment, which are essential for ensuring electrical continuity and integration accuracy in 3D architectures.
• Stealth dicing and SMT assembly, where edge quality, solder volume, and underfill uniformity affect mechanical stability and thermal performance.
We will discuss the limitations of traditional electrical test methods in capturing early-stage process excursions and highlight the role of inline metrology in enabling real-time process control. Emphasis will be placed on non-destructive, high-resolution measurement techniques capable of characterizing buried interfaces and fine structures—essential for ensuring manufacturability and reliability in advanced packaging