Abstract
AI/HPC workloads are expanding rapidly in both volume and complexity. To meet delivery commitments, new advanced packaging processes and factories must reach qualified yield in compressed timeframes, ramp up has become a first order program constraint. In parallel, yield have tightened: multi die assemblies with costly logic and HBM stacks raise the value at risk per unit, meanwhile, process complexity is rising (more build up layers, finer RDL, larger panels), tightening lithography process windows and elevating overlay driven risk. These pressures require an effective and defensible yield monitoring system that can guide decisions during development and provide actionable screening in HVM.
Event Details
| Date | Apr 15 — Apr 15, 2026 |
|---|---|
| Location | Hiroshima, Japan |
| Event | International Conference on Electronic Packaging (ICEP) |
| Presenters |
