Atlas® V System
The Atlas V system is an OCD and thin film metrology tool for high volume manufacturing, enabling FinFET & Gate-All-Around (GAA) logic, DRAM, and 3D NAND device process control.

Product Overview
The Atlas V system combines state of the art optical design with an innovative Ai Diffract™ modeling engine, providing OCD and thin film metrology solutions for measuring complex 3D device structures. The dual channel optical architecture consists of a DUV 4×4 Mueller Matrix (MM) SE and a DUV polarized normal incident reflectometer (NIOCD). Together, they provide rich information for OCD analysis at high precision and high throughput. The Atlas V system is designed to measure the most critical and challenging process steps that include buried features, not visible by CD-SEM and other techniques.
With unique capabilities, such as measuring individual nanowire dimension in a GAA logic device, the Atlas V system is an enabling technology for leading edge device process control.
Applications
- OCD for litho, etch, CVD & CMP process in all device segments
- Local variation
- Asymmetry and tilt
- Common and critical films
- Stress & wafer warpage
Intelligent Line Monitoring & Control with Integrated Metrology
Enhance CMP process control with a connected metrology approach that feeds forward data from standalone OCD or films metrology to integrated metrology, connected through AI-driven analytical software. This approach, powered by advanced modeling and analysis tools, can deliver high-precision, high-throughput results—minimizing or eliminating the need for and cost of new TEM data and enabling accelerated time to solution, faster excursion detection, reduced cost and improved Cpk.

Enhancing CMP Process Control with Intelligent Line Monitoring & Integrated Metrology
As semiconductor manufacturers push the boundaries of performance and functionality—driven by high-performance computing and AI applications—chemical mechanical planarization (CMP) processes increase in intensity complexity. New logic transistor designs, 3D NAND stacking, and DRAM integration introduce more CMP layers and tighter process windows.

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