Dragonfly® G5 System
The Dragonfly G5 system is engineered for inline process control of leading-edge advanced packaging technologies. As the latest generation pattern inspection system in the Dragonfly series, it delivers unparalleled accuracy in detecting submicron defects and performing high-resolution 3D measurements.
Product Overview
Designed to meet the demands of advanced semiconductor technologies, the Dragonfly G5 system is purpose-built to deliver high-performance, reliable inspection and metrology across complex heterogeneous integration processes. Leveraging next generation high speed line scan 2D imaging and custom-engineered objectives, the system achieves over 3X throughput improvement compared to its predecessor, with submicron sensitivity down to 150nm.
Continuing the legacy of innovation, the Dragonfly G5 system introduces a multi-angle illumination channel that significantly improves signal-to-noise ratio for faint defect detection. Combined with powerful AI-driven algorithms, it enhances both the detectability and classification of critical, yield-impacting defects–empowering fabs to maintain quality and accelerate time-to-yield.
The Dragonfly G5 system expands process control flexibility for wafer-to-wafer and die-to-wafer bonding by integrating high-speed IR imaging to detect sub-surface defects. It incorporates the latest generation of 3Di™ technology, extending bump height metrology capabilities to support next-generation microbumps essential for 3D integration. This enables additional inspection and metrology touchpoints across increasingly complex packaging architectures.
Applications
- Hybrid Bonding
- Redistribution Layers (RDL): after develop, after etch
- BS/FS Pad CMP
- TSV Reveal
- Micro bumps and Cu pillars
Featured News
Hybrid Bonding Process Control Solution
Hybrid bonding enables ultra-dense 3D memory interconnects with up to 1,000x more connections than microbumps. Achieving high yield requires stringent process control, including monitoring topography and detecting particles, cracks and voids. Measuring dishing in copper pads provides valuable insight into surface conditions. Together, these process control insights contribute to improved device reliability and performance.
Enabling In-Line Process Control for Hybrid Bonding Applications
As demand grows for high-performance computing (HPC) and AI-driven applications, manufacturers are turning to hybrid bonding to enable the ultra-dense 3D integration required for next-generation chip architectures. This advanced packaging technology presents significant process challenges. Surface preparation must be precisely controlled to eliminate particles, excess recess, and copper pad dishing, all of which can compromise bond quality. During pre-annealing, particle-induced gaps and wide bonding gaps can prevent proper wafer contact. Post-annealing, the formation of dielectric and metal voids introduces further risks to electrical performance and long-term reliability.
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