May 27, 2020 Lake Buena Vista, Florida

Photolithography Solution That Overcomes Significant Die Placement Error For Advanced Packaging

Tong Yang

Presentation at Electronic Components and Technology Conference (ECTC)
11:00am — 10:24pm

As front-end manufacturers of semiconductor devices continue to decrease the size of circuit features to improve electronics functionality and reduce cost, back-end architects are also striving to provide low-cost effective solutions for smaller and more compact package designs. One of the solutions is to employ a more capable lithography system for multi-layer interconnection SIP, where multiple die with different functionality, are combined into a single package. Such a lithography system enables advanced wafer level packaging (WLP) and advanced panel level packaging (PLP); in those processes, the die are pick-and-placed by a robot onto reconstituted wafers or panels, where significant die placement errors are induced. As die become larger and the layouts become tighter, it is essential to ensure reliable photolithography pattern placement for a tight overlay registration between layers, especially when the exposure field size is large such as 59.4mm x 59.4mm.

Presently, the requirements for an advanced packaging photolithography system go beyond the simple inherent system overlay; more advanced features, such as magnification and extended rotation correction are needed to accommodate the mismatch between the feature position/size on substrate and the reticle pattern. In this paper, we introduce a 2X reduction photolithography system with site-by-site magnification (mag) correction and extended site-by-site theta correction features. This technology actively mitigates site-by-site mag errors up to +/-400ppm, and theta errors up to +/-1.65mrad. These advanced features improve the overlay accuracy which leads to increased yield. Futhermore, the paper discusses the impact of this extended correction capability on throughput.