Oct 5 — Oct 8, 2020 Virtual

Performing Sub-micron Defect Inspection on Large 600mm Panels

Woo Young Han

Woo Young Han

Presentation at 53rd International Symposium on Microelectronics (IMAPS 2020)
8:00am — 9:54am

Semiconductor manufacturers are continuously driving efforts to put more computing power and speed into less volume.  At the same time, consumers are demanding devices with more functionality that integrate a variety of interconnected circuit types. The result has been an increasing reliance on advanced packaging technologies that use fab-like processes to integrate multiple chips and to provide the increased I/O capability required.

The demand for higher performance electronics in smaller packages has led to the development of fan-out level packaging.  There is no doubt that fan-out wafer level packaging (FOWLP) and fan-out panel level packaging (FOPLP) are gaining popularity in the industry.  The demand for low cost, smaller packages with high density interconnects for cell phones and wearable devices has been leading the development of fan-out level packaging.

The development of fan-out level packaging is following processes similar to front-end development. Circuitry complexity is growing while critical dimension size is decreasing, which makes inspection and metrology critical steps to maintain process control and high yield. Typical RDL size was around 20µm in the beginning of fan-out level packaging about 15 years ago but typical RDL sizes are 2µm to 4µm in 2019 for both wafer level and panel level fan-out packaging. 

Traditional defect inspection using bright field and dark field illumination has been the dominant inspection method used in front-end and back-end wafer manufacturing. However, traditional inspection methodology has challenges and is not well suited for fan-out level wafers and panels, often resulting in a large number of nuisance defects and missing critical defects.

One of the main differences between the inspections in front-end and fan-out level packaging is noisy grainy metals.  Inspection algorithms are designed to find defects by identifying non-repeating, random patterns from highly repeating patterns and that is why it is not well suited for fan-out level packaging covered with noisy grainy metals. In addition, large topography variation and presence of invisible transparent defects are challenges to traditional inspection methodology.

With RDLs shrinking down to 1µm, performing sub-micron defect inspection is an essential process for fan-out level packaging manufacturing but the traditional sub-micron defect inspection tools for front-end manufacturing simply do not work on large 600mm by 600mm rectangular panels.

This paper describes inspection challenges on fan-out level panels and possible solutions to overcome the challenges.